Semiconductor integrated circuit device operating with low power consumption

ABSTRACT

Transistors having large gate tunnel barriers are used as transistors to be on in a standby state, MIS transistors having thin gate insulating films are used as transistors to be off in the standby state, and main and sub-power supply lines and main and sub-ground lines forming a hierarchical power supply structure are isolated from each other in the standby state so that a gate tunnel current is reduced in the standby state in which a low power consumption is required. In general, a gate tunnel current reducing mechanism is provided for any circuitry operating in a standby state and an active state, and is activated in the standby state to reduce the gate tunnel current in the circuitry in the standby state, to reduce power consumption in the standby state.

RELATED APPLICATIONS

This application is a Divisional of U.S. application Ser. No.11/126,296, filed May 11, 2005, which is a Continuation of U.S.application Ser. No. 10/680,397 filed on Oct. 8, 2003, now U.S. Pat. No.6,911,703, which is a Divisional of U.S. application Ser. No. 09/776,681filed on Feb. 6, 2001, now U.S. Pat. No. 6,635,934, claiming priority ofJapanese Application Nos. 2000-167189, filed Jun. 5, 2000 and2000-261703, filed Aug. 30, 2000, the entire contents of each of whichare hereby incorporated by reference.

BACKGROUND OF THE PRESENT INVENTION

1. Field of the Present Invention

The present invention relates to a semiconductor device includinginsulated gate field effect transistors, referred to as “MIStransistors” hereinafter, as it components, and particularly to aconfiguration for reducing power consumption in a semiconductor devicehaving miniaturized CMOS transistors (P- and N-channel MIS transistors).More particularly, the present invention relates to a structure forsuppressing a gate tunnel current of a miniaturized MIS transistor.

2. Description of the Background Art

In a CMOS semiconductor device, as the size of MIS transistors isreduced, an operation power supply voltage is lowered for ensuringreliability of the transistors and reducing power consumption. Forreducing the sizes of MIS transistors in accordance with lowering of theoperation power supply voltage, values of various transistor parametersare reduced according to a certain scaling rule. According to thescaling rule, it is necessary to reduce a thickness Tox of a gateinsulating film of the MIS transistor, and it is also necessary toreduce an absolute value Vth of a threshold voltage. However, it isdifficult to reduce the absolute value of the threshold voltageaccording to the scaling rule. The threshold voltage is defined as agate-source voltage, which causes a predetermined drain current underapplication of a predetermined drain voltage. If absolute value Vth ofthe threshold voltage is small, a weak inversion layer is formed in achannel region even with a gate-source voltage Vgs being 0 V, and asub-threshold leak current, referred to as an “off-leak current”hereinafter, flows through this inversion layer.

Therefore, such a problem occurs that the off-leak current increases toincrease the standby current in a standby cycle during which MIStransistors are off. Particularly, in a semiconductor device for use ina battery-powered equipment such as a portable equipment, it is greatlyrequired to reduce the off-leak current in view of a lifetime of thebattery.

For reducing the off-leak current, absolute value Vth of the thresholdvoltage can simply be increased. In this case, however, reduction of theoperation power supply voltage cannot achieve an intended effect, andfast operation cannot be ensured. Thus, an MT-CMOS (Multi-ThresholdCMOS) structure has been proposed for reducing the off-leak current inthe standby cycle and for ensuring fast operation.

FIG. 104 shows, by way of example, a structure of an MT-CMOS circuit inthe prior art. In the structure shown in FIG. 104, five invertercircuits IV0-IV4 are cascaded. For these inverter circuits IV0-IV4,there are arranged a main power supply line MVL coupled to a powersupply node, a sub-power supply line SVL coupled to main power supplyline MVL via a switching transistor SWP, a main ground line MGL coupledto a ground node, and a sub-ground line SGL coupled to main ground lineMGL via a switching transistor SWN.

Inverter circuits IV0-IV4 each have a structure of a CMOS inverter, andinclude P-channel MIS transistors P0-P4 and N-channel MIS transistorsN0-N4, respectively. This MT-CMOS circuit has a standby cycle in astandby state and an active cycle in which an input signal changesactually. In the standby cycle, input signal IN is fixed to L-level, andswitching transistors SWP and SWN are kept in the off state in responseto control signals /φ and φ, respectively. Each of switching transistorsSWP and SWN has a threshold voltage relatively large (medium) inabsolute value, M-Th. Each of MIS transistors P0-P4 and N0-N4 ofinverter circuits IV0-IV4 has a threshold voltage of a small absolutevalue, L-Th.

Depending on a logical level of an input signal IN in the standby cycle,a source of each MIS transistor, which is on in the standby cycle, isconnected to main power supply line MVL or main ground line MGL. Morespecifically, sources of MIS transistors P0, P2 and P4 are connected tomain power supply line MVL, and sources of MIS transistors N1 and N3 areconnected to main ground line MGL. A source of each MIS transistor,which is off in the standby cycle, is connected to sub-power supply lineSVL or sub-ground line SGL. More specifically, sources of MIStransistors P1 and P3 are connected to sub-power supply line SVL, andsources of MIS transistors N0, N2 and N4 are connected to sub-groundline SGL. Now, an operation of the MT-CMOS circuit shown in FIG. 104will now be described with reference to a signal waveform diagram ofFIG. 105.

During the standby cycle, input signal IN is at L-level, and controlsignals φ and /φ are at L- and H-levels, respectively. In this state,switching transistors SWP and SWN are off. Switching transistor SWP isan M-Vth transistor, and the off-leak current thereof in the standbystate cycle is small.

In inverter circuits IV0-IV4, MIS transistors P0, P2 and P4 are on, anddo not cause a sub-threshold leak (off-leak) current. Meanwhile, MIStransistors P1 and P3 are off, and cause an off-leak current fromsub-power supply line SVL. The off-leak currents flowing through MIStransistors P1 and P3 flow to main ground line MGL through MIStransistors N1 and N3 in the on state, respectively. However, theoff-leak current flowing through MIS transistors P1 and P3 depends inmagnitude on the off-leak current flowing through switching transistorSWP. Therefore, the voltage level of sub-power supply line SVL reachesan equilibrium state where the off-leak current flowing throughswitching transistor SWP is balanced with the sum of off-leak currentsflowing through MIS transistors P1 and P3. Due to the current flow, thevoltage level of sub-power supply line SVL is lower than power supplyvoltage VCC, and MIS transistors P1 and P3 enters such a state that thegate to source thereof is reverse-biased, and therefore enters a deeperoff state. Accordingly, MIS transistors P1 and P3 can have the off-leakcurrents sufficiently reduced.

Likewise, off-leak currents flow through MIS transistors N0, N2 and N4.These off-leak currents flowing through MIS transistors N0, N2 and N4depend in magnitude on the off-leak current flowing through switchingtransistor SWN. Switching transistor SWN is an M-Vth transistor, and hasa sufficiently small off-leak current so that the off-leak currents ofMIS transistors N0, N2 and N4 can be sufficiently suppressed.

In the above case, the voltage level of sub-ground line SGL reaches anequilibrium state where the sum of off-leak currents flowing through MIStransistors N0, N2 and N4 are balanced with the off-leak current flowingthrough switching transistor SWN, and therefore is higher than groundvoltage GND. In this case, each of MIS transistors N0, N2 and N4 enterssuch a state that the gate to source thereof is reverse-biased, andtherefore enters a deeper off state. Accordingly, MIS transistors N0, N2and N4 can have the off-leak current sufficiently suppressed.

In the active cycle for actually performing an operation, controlsignals φ and /φ are set to H- and L-levels, respectively, and switchingtransistors SWP and SWN are turned off. Responsively, sub-power supplyline SVL is connected to main power supply line MVL, and sub-ground lineSGL is connected to main ground line MGL. Inverter circuits IV0-IV4include L-Vth transistors as components, and therefore, rapidly changetheir output signals in accordance with input signal IN.

As shown in FIG. 104, the power supply line differs in impedance valuedepending on the standby cycle and the active cycle. Thereby, even withthe L-Vth transistors employed as its components, the off-leak currentcan be sufficiently suppressed in the standby cycle, while ensuring fastoperation performance in the active cycle. Accordingly, a CMOS circuitcapable of fast operation with low power consumption can be implemented.

Various parameters such as sizes of the MIS transistors are reducedaccording to a certain scaling rule. The scaling rule stands on thepremise that the gate length of the MIS transistor and the thickness ofthe gate insulating film thereof are reduced at the same scaling ratio.For example, an MIS transistor having a gate length of 0.25 μm(micrometers) generally has a gate insulating film of 5 nm (nanometers)in thickness, and therefore an MIS transistor having a gate length ofabout 0.1 μm has a gate insulating film from about 2.0 to about 2.5 nmin thickness. In the case where the thickness of gate insulating film isreduced in accordance with lowering of the operation power supplyvoltage and is reduced to about 3 nm in accordance with the conditionthat the power supply voltage is 1.5 V or lower, for example, a tunnelcurrent flows through the gate insulating film of MIS transistor in theon state, resulting in a problem of increase in power supply current ofthe transistor in the on state.

FIGS. 106A-106C schematically show energy bands of the MIS transistor,with the gate being a metal gate. Normally, in the MIS structure, a gateis formed of polycrystalline silicon doped with impurities and hasproperties as a semiconductor. For simplicity reason, however, it ishere assumed that the gate is made of a metal. The semiconductorsubstrate region is of the P-type substrate (layer).

As shown in FIG. 106A, it is now assumed that a negative voltage isapplied on the gate. In this state, holes present in the P-typesubstrate are pulled toward the interface between the substrate and theinsulating film. Thereby, the energy band of the P-type substrate isbent upward at the interface between the insulating film and the P-typesubstrate, and a valence band Ev approaches a Fermi level EF. Aconduction band Ec is bent upward at the vicinity of this interface. Inthis case of application of the negative voltage, Fermi level EF of thegate (corresponding to conduction band Ec in the case of apolycrystalline silicon gate) also rises. In this state, the density ofmajority carriers (holes) on the interface is higher than that in theinner portion. This state is called an accumulated state. In this state,the conduction band Ec is bent upward, and a barrier against electronsis high so that the tunneling current through the gate insulating filmdoes not flow.

Where a low positive voltage is applied to the gate as shown in FIG.106B, the Fermi level (conduction band) of the gate lowers so thatconduction band Ec and valence band Ev are bent downward in the P-typesubstrate region at the interface with the insulating film. In thisstate, holes have been located away from the interface to the gateinsulating film so that depletion of majority carriers occurs, and Fermilevel EF on the interface is located substantially in the center of theband. This state, where a majority carrier is not present, is called adepletion state. In this depletion state, a carrier is not present onthe interface, and a tunnel current does not occur.

When a further high positive voltage is applied as shown in FIG. 106C,Fermi level EF of the gate further lowers, and the band bending at thevicinity of the interface occurs to a larger extent. Consequently, Fermilevel EF of the gate exceeds the intermediate value of energy gap Eg atthe vicinity of the interface, and electrons which are minority carriesare accumulated. This state is called an inverted state because theconduction type of the interface is inverted with respect to that of theinterior. This state corresponds to the state where a channel is formedin the MIS transistor. If the gate insulating film has a thickness δ of,e.g., 3 nm in this state, electrons which are minority carriers flowinto the gate through a tunneling phenomenon. Thus, the tunnel currentdirectly flows into the gate from the channel region in the MIStransistor having the channel formed and thus conductive. This tunnelcurrent is called a (direct) gate tunnel current. Similar behaviorsoccur in a structure having an N-type substrate region, except for thata voltage applied to the gate has the opposite polarity and that theenergy band bends in the opposite direction.

In MIS transistor, if the thickness of the gate insulating film isreduced, e.g., to 3 nm, a direct gate current flows from the channelregion to the gate. Consequently, the MT-CMOS circuit such as that shownin FIG. 104 accompanies the following problem. In the standby cycle, atunnel current flows from the channel region to the gate in an on stateMIS transistor, and through-current finally flows from the power supplynode to the ground node so that the current consumption in the standbycycle increases.

FIG. 107 shows a path of a tunnel current in the MT-CMOS circuit shownin FIG. 104 in the standby cycle.

FIG. 107 shows a structure of a portion including inverter circuits IV1and IV2. In inverter circuit IV1, MIS transistor N1 has a source and aback gate connected together to main ground line MGL, and MIS transistorP1 has a source connected to a sub-power supply line (not shown). Ininverter circuit IV2, MIS transistor P2 has a back gate and a sourceconnected together to main power supply line MVL, and MIS transistor N2has a source connected to a sub-ground line (not shown).

In the standby cycle, inverter circuit IV1 is supplied with a signal atH-level. Therefore, the output signal of inverter circuit IV1 is atL-level or the level of ground voltage GND in the standby cycle, and MIStransistor P2 in inverter circuit IV2 is on. In MIS transistor P2, atunneling current It flows from the substrate region to the gate, andfurther flows to main ground line MGL through MIS transistor N1. Asindicated by broken line in FIG. 107, the gate tunnel current of MIStransistor P2 causes a through current flowing from main power supplyline MVL to main ground line MGL.

FIG. 108 shows a structure of a portion including inverter circuits IV2and IV3 of the MT-CMOS circuit shown in FIG. 104. In the standby cycle,inverter circuit IV2 is supplied with a signal at L-level. The sourcesof MIS transistors P2 and N3 are connected to main power supply line MVLand main ground line MGL, respectively, while the sources of MIStransistors N2 and P3 are connected to the sub-ground line and sub-powersupply line (both not shown in FIG. 108), respectively. In this state inthe standby cycle, MIS transistor P2 is on, and supplies a current tothe gate of MIS transistor N3 from main power supply line MVL.

MIS transistor N3 is on, and therefore gate tunnel current It flowsthrough MIS transistor N3 (through the source region and the back gateregion) to main ground line MGL. When the back gate of MIS transistor N3is biased to a voltage level different from ground voltage GND, gatetunnel current It of MIS transistor N3 flows from this channel regionthrough the source region. In this case, therefore, gate tunnel currentIt likewise causes a though current flowing from main power supply lineMVL to main ground line MGL.

This gate tunnel current is nearly equal to the off-leak current whenthe gate oxide film has a thickness of about 3 nm or less. If the gateoxide film has a thickness smaller than about 3 nm, the gate tunnelcurrent exceeds the off-leak current. Therefore, in the case where theoperating power supply voltage is lowered and the thickness of gateinsulating film is reduced according to the scaling rule, this gatetunnel current cannot be neglected and causes a problem of increase incurrent consumption in the standby cycle.

A gate tunnel current J approximately satisfies the relationshipexpressed by the following formula:

J˜E·exp[−Tox·A·√φ],

where φ represents a height of a barrier at the interface with the gateinsulating film, and is approximately expressed by a difference betweenthe Fermi level and the surface potential φs at the interface, A is aconstant depending on an impurity concentration (an effective mass of anelectron) of the semiconductor substrate in the channel region, and Erepresents an electric field applied to the gate insulating film. Thebarrier Height φ is a function of a dielectric constant εi and thicknessTox of the gate insulating film. Therefore, if a tunnel current startsto flow at the gate oxide film thickness of 3 nm with the gateinsulating film formed of silicon oxide, a gate tunnel current likewiseflows through the gate insulating film, which provides a barrier equalto that by the silicon oxide film of 3 nm in thickness. As the gateinsulating film, there is a silicon nitride oxide film, other than thesilicon oxide film (silicon dioxide film).

As described above, with the miniaturized transistors as components,there arises a problem that the gate tunnel current of the MIStransistor becomes substantially equal to or larger than the off-leakcurrent in the standby, and the current consumption in the standby cyclecannot be reduced.

SUMMARY OF THE PRESENT INVENTION

An object of the present invention is to provide a semiconductor device,which can sufficiently suppress current consumption in the standbystate, and is suitable to a high integration.

Another object of the present invention is to provide a semiconductordevice, in which a gate tunnel current of an MIS transistor can besufficiently suppressed in the standby state.

A semiconductor device according to the present invention includes: afirst power supply node, a logic gate receiving a voltage on a firstpower supply line as one operation power supply voltage, for performinga predetermined operation, and a first switching transistor connectedbetween the first power supply node and the first power supply line, andbeing selectively turned on in response to an operation mode instructingsignal instructing an operation mode of the logic gate. The logic gateincludes, as its components, an MIS transistor having a first gatetunnel barrier, and the first switching transistor has a gate tunnelbarrier greater than the gate tunnel barrier of the MIS transistor ofthe logic gate.

According to a second aspect of the present invention, a semiconductordevice includes a first MIS transistor connected between a first powersupply node and a first output node and receiving an input signal on agate thereof, and a second MIS transistor connected between the outputnode and a second power supply node and receiving the input signal on agate thereof. The first MIS transistor is turned on in accordance withthe input signal in a standby cycle, and has a first gate tunnelbarrier. The second MIS transistor is turned off in accordance with theinput signal in the standby cycle, and has a gate tunnel barrier smallerthan the first gate tunnel barrier.

According to a third aspect of the present invention, a semiconductordevice includes a first MIS transistor connected between a first powersupply node and a first output node and receiving an input signal on agate thereof, a second MIS transistor connected between the first outputnode and a second power supply node and receiving the input signal on agate thereof, and a control circuit for reducing leakage amounts of gatetunnel currents of the first and second MIS transistors in the standbycycle below those in an active cycle.

According to a fourth aspect of the present invention, a semiconductordevice includes a first MIS transistor connected between a first powersupply node and a first output node, having a first gate tunnel barrierand receiving an input signal on a gate thereof, a second MIS transistorconnected between the first output node and a sub-power supply node,receiving the input signal on a gate thereof to be turned oncomplementarily to the first MIS transistor, and a first switchingtransistor connected between the sub-power supply node and a secondpower supply node and being selectively turned on in response to anoperation cycle instructing signal. The second MIS transistor has asecond gate tunnel barrier smaller than the first gate tunnel barrier.

According to a fifth aspect of the present invention, a semiconductordevice includes a first switching transistor connected between a powersupply node and a power supply line and being selectively turned on inresponse to an operation cycle instructing signal, a gate circuitreceiving a voltage on the power supply line as one operation powersupply voltage, for performing a predetermined processing, a replicacircuit including elements formed by proportionally scaling down thegate circuit and the first switching transistor, and a transmittingcircuit for transmitting an output voltage of the replica circuit to thepower supply line in accordance with the operation cycle instructingsignal. The scaled down gate circuit of the replica circuit receives thevoltage on the output node as one operation power supply voltage, andthe scaled down transistor of the first switching transistor supplies avoltage from the power supply node to the output node.

According to a sixth aspect of the present invention, a semiconductordevice includes a first switching transistor connected between a firstpower supply node and a first power supply line and being selectivelyturned on in response to an operation cycle instructing signal, a firstgate circuit receiving a voltage on the first power supply line as oneoperation power supply voltage, a second switching transistor connectedbetween a second power supply node and a second power supply line, andbeing selectively turned on in response to the operation cycleinstructing signal, and a second gate circuit receiving a voltage on thesecond power supply line as one operation power supply voltage. Thefirst and second gate circuits include MIS transistors as theircomponents, and have the same structure.

According to a seventh aspect of the present invention, a semiconductordevice includes a gate circuit including first and second transistorseach having an SOI (Silicon On Insulator) structure, and effectingpredetermined processing on an input signal for outputting, and a biasvoltage applying circuit for applying a bias voltage to body regions ofthe first and second transistors of the gate circuit. The input signalapplied to the gate circuit is at a predetermined logical level in astandby cycle, and each of first and second transistors has a gateinsulating film having a thickness not exceeding 3 nanometers. The biasvoltage applying circuit sets a bias of the body region of at least thetransistor in the off state out of the first and second transistors inthe standby cycle to be deeper than that in an active cycle.

According to an eighth aspect of the present invention, a semiconductordevice includes a gate circuit including first and second MIStransistors each having an SOI (Silicon On Insulator) structure, andeffecting a predetermined logical processing on an input signal foroutputting, and a bias voltage applying circuit for applying a biasvoltage to body regions of the first and second MIS transistors. Thebias voltage applying circuit sets biases of the body regions of thefirst and second transistors to be deeper in the standby cycle thanthose in an active cycle.

According to a ninth aspect of the present invention, a semiconductordevice includes a first MIS transistor connected between a first powersupply node and an output node and receiving an input signal on a gatethereof, and a second MIS transistor connected between the output nodeand a second power supply node and receiving the input signal on a gatethereof. A logical level of the input signal in a standby cycle ispredetermined, and the first MIS transistor is turned on in accordancewith the input signal in the standby cycle, and is formed of an MIStransistor of a buried channel type.

According to a tenth aspect of the present invention, a semiconductordevice includes a first MIS transistor connected between a first powersupply node and an output node and receiving an input signal on a gatethereof, and a second MIS transistor connected between an output nodeand a second power supply node and receiving the input signal on a gatethereof. The logical level of the input signal in a standby cycle ispredetermined, and the first MIS transistor is turned on in response tothe input signal in the standby cycle, and is an MIS transistor of adepleted gate type.

According to an eleventh aspect of the present invention, asemiconductor device includes a latch circuit for latching an appliedsignal, and a gate circuit for effecting a predetermined processing on alatch output signal of the latch circuit. The latch circuit is formed ofan MIS transistor having a first gate tunnel barrier. The gate circuitis formed of an MIS transistor having a gate tunnel barrier smaller thanthe first gate tunnel barrier.

According to a twelfth aspect of the present invention, a semiconductordevice includes a first latch circuit for latching an applied signal inan active cycle, a second latch circuit for latching an applied signalin a standby cycle, and a transfer circuit transferring a latchingsignal of the first latch circuit to the second latch circuit inresponse to transition of an operation cycle instructing signal from anactive cycle instruction to a standby cycle instruction, andtransferring a latching signal of the second latch circuit to the firstlatch circuit in response to transition of the operation cycleinstructing signal from the standby instruction to the active cycleinstruction. The first latch circuit has a first gate tunnel barrier,and the second latch circuit has a gate tunnel barrier larger than thefirst gate tunnel barrier.

According to a thirteenth aspect of the present invention, asemiconductor device includes a precharge transistor for precharging aprecharge node to a predetermined voltage level in response toactivation of a precharge instructing signal, and a gate circuit coupledto the precharge node, being in a standby state in an active state ofthe precharge instructing signal, and driving the precharge node inaccordance with an applied signal in an inactive state of the prechargeinstructing signal. The precharge transistor has a first gate tunnelbarrier, and an MIS transistor of the gate circuit has a second gatetunnel barrier greater than the first gate tunnel barrier.

According to a fourteenth aspect of the present invention, asemiconductor device has a precharge transistor being activated toprecharge a precharge node to a predetermined voltage for apredetermined time upon transition from a standby cycle to an activecycle, and a gate circuit for driving the precharge node in accordancewith an applied signal in the active cycle. The gate circuit has thesame, first gate tunnel barrier as the precharge transistor. The firstgate tunnel barrier has a height equal to or greater than that of a gatetunnel barrier provided by a silicon oxide film of 3 nm in thickness.

According to a fifteenth aspect of the present invention, asemiconductor device includes a plurality of memory cells requiringrefresh of storage data, a timer circuit being activated in a refreshmode to generate a refresh request instructing refreshing of the storeddata of the plurality of memory cells at predetermined intervals, arefresh address counter for generating a refresh address specifying amemory cell row of the plurality of memory cells to be refreshed, andrefresh-related circuitry for refreshing the stored data of the memorycells specified by the refresh address among the plurality of memorycells. The timer circuit and the refresh address counter include MIStransistors having a first gate tunnel barrier as components, and therefresh-related circuitry includes, as a component, an MIS transistorhaving a second gate tunnel barrier of a height not exceeding that ofthe first gate tunnel barrier.

According to a sixteenth aspect of the present invention, asemiconductor device includes a logic circuit including an insulatedgate field effect transistor as its component, a latch circuit providedcorresponding to an internal node of the logic circuit for latching asignal on the corresponding internal node, and a transfer path coupledto the latch circuit for transferring the signal of the latch circuit.At least the logic circuit is set to a state of having a gate tunnelcurrent reduced in a standby state.

According to a seventeenth aspect of the present invention, asemiconductor device includes a plurality of internal circuits formed ofMIS transistors, and performing predetermined operations when madeactive, an activation control circuit responsive to an internal circuitdesignating signal designating an internal circuit to be activated amongthe plurality of internal circuits for generating an internal circuitactivating signal for activating the designated internal circuit, and acurrent control circuit responsive to an operation mode instructingsignal and the internal circuit activating signal for holding a gatetunnel current of the MIS transistor of the internal circuit in theinactive state among the plurality of internal circuits to be smallerthan that of the MIS transistor of the internal circuit in the activestate. The operation mode instructing signal designates an active cycleof enabling the plurality of internal circuits and a standby cycle ofdisabling the plurality of internal circuits.

According to an eighteenth aspect of the present invention, asemiconductor device includes a normal array having a plurality ofnormal memory cells, a redundant array having spare memory cells forrepairing a defective normal memory cell having a defect in the normalarray, a normal access circuit for accessing a selected memory cell inthe normal array, a spare access circuit for accessing a spare memorycell in the redundant array, and a power supply control circuit fordetermining a gate tunnel current of an MIS transistor of the inactivecircuit out of the spare access circuit and the normal access circuit tobe smaller than the gate tunnel circuit of the MIS transistor of theactive circuit.

If a gate tunnel current may occur in an MIS transistor, measures aretaken for the MIS transistor, e.g., of increasing the height of the gatetunnel barrier or cutting off the current flowing path. For the MIStransistors through which the gate tunnel current may not occur, MIStransistors having sizes reduced according to a scaling rule is used.Owing to these measures, the semiconductor device which can operate fastwith low current consumption can be implemented.

When the circuit is to be disabled, the gate tunnel current of the MIStransistor forming the circuit is reduced, or the power supply voltageis powered down. Thereby, the current consumption of the disabledcircuit can be reduced, and the semiconductor device operating with lowcurrent consumption can be implemented.

The foregoing and other objects, features, aspects and advantages of thepresent invention will become more apparent from the following detaileddescription of the present invention when taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A shows a structure of a semiconductor device according to a firstembodiment of the present invention, and FIG. 1B is a signal waveformdiagram representing an operation of the semiconductor device shown inFIG. 1A;

FIG. 2A shows a structure of a modification of the first embodiment ofthe present invention, and FIG. 2B is a signal waveform diagramrepresenting an operation of the device shown in FIG. 2A;

FIG. 3A shows a structure of a semiconductor device according to asecond embodiment of the present invention, and FIG. 3B is a signalwaveform diagram representing an operation of the device shown in FIG.3A;

FIG. 4 shows a leak current path in the device shown in FIG. 3A;

FIG. 5 shows a structure of a semiconductor device according to a thirdembodiment of the present invention;

FIG. 6 is a signal waveform diagram representing an operation of thesemiconductor device shown in FIG. 5;

FIG. 7 schematically shows a cross sectional structure of thesemiconductor device shown in FIG. 5;

FIG. 8A schematically shows a cross sectional structure of an MIStransistor in the third embodiment of the present invention, and FIG. 8Bshows a gate-substrate capacitance of the MIS transistor shown in FIG.8A;

FIG. 9 schematically shows a structure of an N-well bias circuit shownin FIG. 7;

FIG. 10 schematically shows a structure of a P-well bias circuit shownin FIG. 7;

FIG. 11 schematically shows a structure of a modification of the thirdembodiment of the present invention;

FIG. 12 is a signal waveform diagram representing an operation of thedevice shown in FIG. 11;

FIG. 13 shows a structure of a second modification of the thirdembodiment of the present invention;

FIG. 14 is a signal waveform diagram representing an operation of thedevice shown in FIG. 13;

FIG. 15 schematically shows a cross sectional structure of an MIStransistor in the semiconductor device shown in FIG. 13;

FIG. 16 schematically shows a structure of a semiconductor deviceaccording to a fourth embodiment of the present invention;

FIG. 17 is a signal waveform diagram representing an operation of thedevice shown in FIG. 16;

FIG. 18 schematically shows a modification of the fourth embodiment ofthe present invention;

FIG. 19 shows a structure of a semiconductor device according to a fifthembodiment of the present invention;

FIG. 20 is a signal waveform diagram representing an operation of thedevice shown in FIG. 19;

FIGS. 21A-21C show structures of MIS transistors having great gatetunnel barriers, respectively;

FIG. 22 shows a structure of a semiconductor device according to a sixthembodiment of the present invention;

FIG. 23 is a signal waveform diagram representing an operation of thedevice shown in FIG. 22;

FIG. 24 shows a structure of a voltage adjusting circuit shown in FIG.22;

FIG. 25A shows a structure of a first modification of the sixthembodiment of the present invention, and FIG. 25B is a signal waveformdiagram representing an operation of the device shown in FIG. 25A;

FIGS. 26-29 shows structures of first to fourth modifications of thesixth embodiment of the present invention, respectively;

FIG. 30 schematically shows a cross sectional structure of asemiconductor device according to a seventh embodiment of the presentinvention;

FIG. 31A schematically shows a plan layout of an MIS transistor shown inFIG. 30, and FIG. 31B schematically shows a cross sectional structure ofthe transistor shown in FIG. 31A;

FIG. 32 shows a modification of the plan layout of the MIS transistorshown in FIG. 30;

FIG. 33A shows a structure of a semiconductor device of a seventhembodiment of the present invention, and FIG. 33B is a signal waveformdiagram representing an operation of the device shown in FIG. 33A;

FIG. 34A shows a modification of the seventh embodiment of the presentinvention, and FIG. 34B is a signal waveform diagram representing anoperation of the device shown in FIG. 34A;

FIG. 35 schematically shows a cross sectional structure of an MIStransistor used in an eighth embodiment of the present invention;

FIG. 36A schematically shows a channel impurity concentration profile ofa buried channel N-type MIS transistor with a P+ gate, and FIG. 36Bschematically shows an impurity concentration profile of a channelregion of a surface channel N-type MIS transistor with an N+ gate;

FIG. 37A schematically shows an impurity concentration profile of achannel region of a buried channel P-type MIS transistor with an N+gate, and FIG. 37B shows an impurity concentration profile of a channelregion of a surface channel P-type MIS transistor with a P+ gate;

FIG. 38A shows a structure of a semiconductor device according to aneighth embodiment of the present invention, and FIG. 38B is a signalwaveform diagram representing an operation of the semiconductor deviceshown in FIG. 38A;

FIG. 39A shows a modification of the eighth embodiment of the presentinvention, and FIG. 39B is a signal waveform diagram representing anoperation of the device shown in FIG. 39A;

FIGS. 40A and 40B schematically show a sectional structure of an MIStransistor used in a ninth embodiment of the present invention;

FIG. 41 shows a structure of a semiconductor device according to theninth embodiment of the present invention;

FIG. 42 shows a modification of the ninth embodiment of the presentinvention;

FIG. 43 shows a structure of a semiconductor device according to a tenthembodiment of the present invention;

FIG. 44 shows a modification of the tenth embodiment of the presentinvention;

FIG. 45 is a signal waveform diagram representing an operation of thesemiconductor device shown in FIG. 44;

FIG. 46 shows a structure of a second modification of the tenthembodiment of the present invention;

FIG. 47 schematically shows a structure of a semiconductor deviceaccording to an eleventh embodiment of the present invention;

FIG. 48 is a signal waveform diagram representing an operation of thesemiconductor device shown in FIG. 47;

FIG. 49A schematically shows a structure of a portion for generating acontrol signal in the semiconductor device shown in FIG. 47, and FIG.49B is a signal waveform diagram representing an operation of thecontrol signal generating portion shown in FIG. 49A;

FIG. 50 shows a modification of the operation of the semiconductordevice shown in FIG. 49A;

FIG. 51A shows a modification of a control signal generating portion forthe semiconductor device shown in FIG. 47, and FIG. 51B is a signalwaveform diagram representing an operation of the device shown in FIG.51A;

FIG. 52 shows a modification of the operation of the semiconductordevice shown in FIG. 47;

FIG. 53 schematically shows a structure of a portion for generating acontrol signal shown in FIG. 52;

FIG. 54 is a signal waveform diagram representing still anotheroperation of the semiconductor device shown in FIG. 47;

FIG. 55 schematically shows a structure of a portion generating acontrol signal shown in FIG. 54;

FIG. 56A shows a modification of the semiconductor device of theeleventh embodiment of the present invention, and FIG. 56B is a signalwaveform diagram representing an operation of the semiconductor deviceshown in FIG. 56A;

FIG. 57A shows a structure of a transfer instructing signal generatingportion of the semiconductor device shown in FIG. 56A, and

FIG. 57B is a signal waveform diagram representing an operation of thecircuit shown in FIG. 57A;

FIG. 58 is a signal waveform diagram representing still anotheroperation of the semiconductor device according to the eleventhembodiment of the present invention;

FIG. 59A shows a structure of a semiconductor device according to antwelfth embodiment of the present invention, FIG. 59B is a signalwaveform diagram representing an operation of the device shown in FIG.59A, and FIG. 59C shows a general form of the semiconductor device shownin FIG. 59A;

FIG. 60A shows a structure of a first modification of the twelfthembodiment of the present invention, and FIG. 60B is a signal waveformdiagram representing an operation of the device shown in FIG. 60A;

FIG. 61 shows a structure of a portion for generating a prechargeinstructing signal of the device shown in FIG. 60A;

FIG. 62 is a signal waveform diagram showing a modification of theoperation of the semiconductor device of the twelfth embodiment of thepresent invention;

FIG. 63 schematically shows a structure of a precharge instructingsignal generating portion having an operation sequence shown in FIG. 62;

FIG. 64 shows a general structure of a second modification of thetwelfth embodiment of the present invention;

FIG. 65 is a signal waveform showing a third operation sequence of thesemiconductor device according to the twelfth embodiment of the presentinvention;

FIG. 66 shows a structure of a portion for generating a prechargeinstructing signal shown in FIG. 65;

FIG. 67A shows a structure of a semiconductor device according to afourth modification of the twelfth embodiment of the present invention,and FIG. 67B is a signal waveform diagram representing an operation ofthe device shown in FIG. 67A;

FIG. 68 schematically shows a structure of a portion generating aprecharge instructing signal shown in FIG. 67A;

FIG. 69 shows a structure of a fifth modification of the twelfthembodiment of the present invention;

FIG. 70 shows a general structure of the fourth and fifth modificationsof the twelfth embodiment of the present invention;

FIG. 71 shows a structure of a sixth modification of the twelfthembodiment of the present invention;

FIG. 72 is a signal waveform diagram representing an operation of thesemiconductor device shown in FIG. 71;

FIG. 73 schematically shows a structure of a portion generating acontrol signal shown in FIG. 72;

FIG. 74A schematically shows a structure of a semiconductor deviceaccording to a thirteenth embodiment of the present invention, and FIG.74B shows a structure of a refresh address counter shown in FIG. 74A;

FIG. 75 schematically shows a structure of a first modification of thethirteenth embodiment of the present invention;

FIG. 76 schematically shows a structure for control of the semiconductordevice shown in FIG. 75;

FIG. 77 schematically shows a structure of a second modification of thethirteenth embodiment of the present invention;

FIG. 78 is a signal waveform diagram representing an operation of thedevice shown in FIG. 77;

FIG. 79 schematically shows a structure of a portion for generating asignal shown in FIG. 78;

FIG. 80 schematically shows a structure of a third modification of thethirteenth embodiment of the present invention;

FIG. 81 schematically shows a structure of a portion for generating acontrol signal shown in FIG. 80;

FIG. 82 schematically shows a structure of a fourth modification of thethirteenth embodiment of the present invention;

FIG. 83 schematically shows a whole structure of a semiconductor deviceaccording to a fourteenth embodiment of the present invention;

FIG. 84 schematically shows a structure of a test and power supplycontrol circuit shown in FIG. 83;

FIG. 85 schematically shows a structure of a register circuit shown inFIG. 83;

FIG. 86 is a signal waveform diagram representing an operation of theregister circuit shown in FIG. 85;

FIG. 87 shows a more specific structure of the test and power supplycontrol circuit shown in FIG. 83;

FIGS. 88 to 91 show structures of first to fourth modifications of thefourteenth embodiment of the present invention, respectively;

FIG. 92 schematically shows a structure of a test controller shown inFIG. 91;

FIG. 93 schematically shows a whole structure of a semiconductor deviceaccording to a fifteenth embodiment of the present invention;

FIG. 94 schematically shows a structure of a portion corresponding toone row block of the semiconductor device shown in FIG. 93;

FIG. 95 schematically shows structures of a block row decoder and a wordline driver shown in FIG. 94;

FIG. 96 schematically shows a structure of a portion providedcorresponding to one column block of the semiconductor device shown inFIG. 93;

FIG. 97 schematically shows a structure of a first modification of thefifteenth embodiment of the present invention;

FIG. 98 schematically shows a structure of a main portion of asemiconductor device according to a sixteenth embodiment of the presentinvention;

FIG. 99 schematically shows a structure of a first modification of thesixteenth embodiment of the present invention;

FIG. 100 schematically shows a structure of a second modification of thesixteenth embodiment of the present invention;

FIG. 101A schematically shows a structure of a third modification of thesixteenth embodiment of the present invention, and FIG. 101B is a signalwaveform diagram representing an operation of the circuit shown in FIG.101A;

FIG. 102 schematically shows a structure of a fourth embodiment of thesixteenth embodiment of the present invention;

FIG. 103 is a signal waveform diagram representing an operation of thecircuit shown in FIG. 102;

FIG. 104 shows, by way of example, a structure of a semiconductor devicein the prior art;

FIG. 105 is a signal waveform diagram representing an operation of thesemiconductor device shown in FIG. 104;

FIGS. 106A-106C schematically show structures of energy bands in anaccumulated state, a depleted state and an inverted state of anN-channel MIS transistor, respectively;

FIG. 107 shows a gate tunnel current path in a conventionalsemiconductor device; and

FIG. 108 shows another path for the gate tunnel current in theconventional semiconductor device.

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment

FIG. 1A schematically shows a structure of a semiconductor deviceaccording to a first embodiment of the present invention. Referring toFIG. 1A, the semiconductor device includes cascaded CMOS invertercircuits IV0-IV4. Each of CMOS inverter circuits IV0-IV4 includes aP-channel MIS transistor PQ and an N-channel MIS transistor NQ as itscomponents. Each of MIS transistors PQ and NQ has a gate insulating filmhaving a sufficiently reduced thickness Tox that provides a gate tunnelbarrier similar to or lower than a gate tunnel barrier provided, e.g.,by a silicon oxide film of 3 nm in thickness. The previous formula ofthe gate tunnel current J includes the gate insulating film thicknessTox and the barrier height φ as parameters, and therefore, the “gatetunnel barrier” is defined here and hereinafter as being given by aproduct of thickness Tox of the gate insulating film and a square rootof barrier height φ. The barrier height φ is expressed by a differencebetween a Fermi level and a surface potential in a so-called bandbending. Usually, this barrier height φ is approximately expressed bythe following expression.

φ=c2·φG+c3,

where φG represents a work function of a gate electrode, and c2 and c3are expressed by functions of a dielectric constant of the gateinsulating film, thickness Tox of the gate insulating film and others.

Each of CMOS inverter circuits IV0-IV4 commonly receives the voltages onsub-power supply line 3 and sub-ground line 4 as its operation powersupply voltages. Sub-power supply line 3 is connected to a main powersupply node 1 via a switching transistor SW1. Sub-ground line 4 isconnected to a main ground node 2 via a switching transistor SW2.Switching transistors SW1 and SW2 each are similar in gate insulationfilm thickness to MIS transistors PQ and NQ, and have sufficiently greatgate tunnel barrier. Switching transistors SW1 and SW2 are sufficientlylarger in current drive capability than MIS transistors PQ and NQ, forsufficiently supplying the operation currents to CMOS inverter circuitsIV0-IV4 in the active cycle. Thus, these switching transistors SW1 andSW2 have sufficiently increased channel widths, respectively.

Switching transistors SW1 and SW2 are selectively turned on and off inresponse to control clock signals /φ and φ, respectively. Control clocksignals φ and /φ turn on switching transistors SW1 and SW2,respectively, in the active cycle in which CMOS inverter circuitsIV0-IV4 actually operate. In the standby cycle in which CMOS invertercircuits IV0-IV4 are in a standby state, control clock signals φ and /φturn off switching transistors SW1 and SW2, respectively.

Referring to FIG. 1A, control clock signals φ and /φ are at H- andL-levels in the active cycle, as shown in a signal waveform diagram ofFIG. 1B, and switching transistors SW1 and SW2 are turned on to couplethe power supply node (main power supply line) 1 to sub-power supplyline 3 and sub-ground line 4 to the main ground node 2, respectively.Switching transistors SW1 and SW2 have sufficiently large current supplycapabilities. Each of CMOS inverter circuits IV0-IV4 includes, as itscomponents, MIS transistors PQ and NQ each having a gate insulating filmof a sufficiently reduced thickness. MIS transistors PQ and NQ areminiaturized along the scaling rule in accordance with operation powersupply voltage VCC, and can operate fast.

In the standby state, as shown in FIG. 1B, control signals φ and /φ areat L- and H-levels, respectively, and switching transistors SW1 and SW2are rendered off. Switching transistor SW1 receives control clock signal/φ at power supply voltage VCC level on its gate. Switching transistorSW2 receives control clock signal φ at the ground voltage level on itsgate. Therefore, switching transistors SW1 and SW2 are in a depletionstate, in which a depletion layer expands in a channel region of each ofswitching transistors SW1 and SW2, so that a reduced voltage is appliedto a gate capacitance of each of switching transistors SW1 and SW2. Thisis because a depletion layer capacitance is connected in series to thegate capacitance, and a voltage between the gate electrode and thesubstrate region is capacitance-divided by the gate capacitance and thedepletion layer capacitance.

Accordingly, a tunnel current hardly flows between the substrate regionand the gate electrode, and a gate tunnel current merely flows in anoverlap region where the drain region and the gate electrode overlapwith each other. This current is smaller in magnitude by about twoorders than the gate tunnel current flowing between the channel regionand the gate electrode, and the gate tunnel currents of switchingtransistors SW1 and SW2 can be made sufficiently small in the standbycycle.

In CMOS circuits IV0-IV4, MIS transistors PQ and NQ are connected tosub-power supply line 3 and sub-ground line 4, respectively. Currentswhich flow under this state are only leak currents (gate tunnel currentsand sub-threshold currents) flowing through switching transistors SW1and SW2 as well as leak currents in CMOS inverter circuits IV0-IV4.Balance is kept between the voltage levels of sub-power supply line 3and the sub-ground line 4 when balance is kept between the leak currentsflowing through switching transistors SW1 and SW2 and the leak currentsflowing through CMOS inverter circuits IV0-IV4.

In this state, switching transistor SW2 is off, and the gate tunnelcurrent of MIS transistor NQ is sufficiently suppressed even when a gatetunnel current flows through MIS transistor NQ to sub-ground line 4.Likewise, in the case where a gate tunnel current flows through MIStransistor PQ, sub-power supply line 3 is coupled to main power supplynode 1 via switching transistor SW1, and the gate tunnel current flowingthrough MIS transistor PQ is sufficiently suppressed by switchingtransistor SW1. Thereby, switching transistors SW1 and SW2 caneffectively cut off the gate tunnel current flow between power supplynode 1 and ground node 2, and the current consumption in the standbystate can be reduced.

As compared to a structure in which CMOS inverter circuits IV0-IV4 areconnected directly to power supply node 1 and ground node 2, switchingtransistors SW1 and SW2 which are made off in the standby cycle cansufficiently suppress the gate tunnel currents.

[Modification]

FIG. 2A shows a structure of a modification of the first embodiment ofthe present invention. In the structure shown in FIG. 2A, each of thegate insulating films of MIS transistors PQ and NQ included in invertercircuits IV0-IV4 has a thickness Tox1 corresponding to the silicon oxidefilm thickness of 3 nm. A switching transistor SW3 connected betweenpower supply node 1 and sub-power supply line 3 has a gate insulatingfilm thickness Tox2 that is greater than thickness Tox1 of the gateinsulating films of MIS transistors PQ and NQ. A switching transistorSW4 connected between sub-ground line 4 and ground node 2 likewise has agate insulating film of a thickness, Tox2. Structures other than theabove are substantially the same as those shown in FIG. 1A, and thecorresponding portions are allotted with the same reference numbers.

As shown in a signal waveform diagram of FIG. 2B, control clock signalsφ and /φ attains inactive and active states depending on the active andthe standby cycles of inverter circuits IV0-IV4. Switching transistorsSW3 and SW4 are formed of MIS transistors. In switching transistors SW3and SW4, the thickness Tox of the gate insulating film is increased tothe thickness Tox2, and the gate tunnel barrier increases so that a gatetunnel current is suppressed. As the thickness of the gate insulatingfilm increases, the absolute values of threshold voltages of switchingtransistors SW3 and SW4 increase so that sub-threshold currents(off-leak currents) are also suppressed. When inverter circuits IV0-IV4are in a standby state, the off-leak currents of the switchingtransistors SW3 and SW4 are suppressed, and thereby the gate tunnelcurrents in inverter circuits IV0-IV4 are suppressed because the gatetunnel currents of the inverters IV0-IV4 depend on the off-leak currentsof switching transistors SW3 and SW4.

In the structure shown in FIGS. 1A and 2A, a control circuit whichgenerates control clock signals φ and /φ is required to include acomponent having a adequately thick gate insulating film. This is forthe following reasons. In switching transistors SW1-SW4, the gate tunnelcurrent may flow, and the path through which the through current due tothe gate tunnel current flows may be formed between the power supplynode and the ground node. For preventing the through current due to thegate tunnel current in the clock control circuit, the MIS transistorhaving a thick gate insulating film has to be used in the clock controlcircuit, to suppress the through current due to the gate tunnel current.

In the structure where switching transistors SW3 and SW4 are used, thegate tunnel current is sufficiently suppressed owing to the thick gateinsulating films thereof. Therefore, it is possible to reduce thethickness of the gate insulating film of the MIS transistor in thecircuit for generating control clock signals φ and /φ.

According to the first embodiment of the present invention, as describedabove, a CMOS circuit having sufficiently thin gate insulating films arecoupled to the power supply node and the ground node via the switchingtransistors which are off in the standby cycle. In the standby cycle,only the off-leak currents of switching transistors is a current sourcefor the gate tunnel current in the CMOS circuit, and the gate tunnelcurrent can be suppressed more significantly than the case where theCMOS circuit is directly connected to the power supply node and theground node.

Second Embodiment

FIG. 3A schematically shows a structure of a semiconductor deviceaccording to a second embodiment of the present invention. In FIG. 3,four CMOS inverter circuits are cascaded. These CMOS inverter circuitsare directly coupled to power supply node 1 and ground node 2. Morespecifically, each of P-channel MIS transistors PQ1-PQ4 has a sourcecoupled to power supply node 1, and each of N-channel MIS transistorsNQ1-NQ4 has a source coupled to ground node 2.

Input signal IN is held at L-level in the standby state and is driven toH-level in the active cycle, as shown in FIG. 3B. In accordance with thelogical level of input signal IN in the standby cycle, the thickness ofthe gate insulating film is set to the large value, the thickness Tox2in each of MIS transistors PQ1, PQ3, NQ2 and NQ4, which are on in thestandby state. In MIS transistors NQ1, PQ2, NQ3 and PQ4 which are off inthe standby cycle, the thickness of each gate insulating film is set tothe thickness, Tox1. In the case of a silicon oxide film, thickness Tox1is equal to 3 nm (nanometers).

In the structure shown in FIG. 3A, MIS transistors PQ1, NQ2, PQ3 and NQ4which are on in the standby cycle are large in gate insulating filmthickness, and are high in the gate tunnel barrier so that the gatetunnel current in the standby cycle can be sufficiently suppressed. Inthe structure shown in FIG. 3A, P-channel MIS transistor (transistorPQ1, for example) is on in accordance with input signal IN in thestandby state, as shown in FIG. 4. However, the gate insulating film ofthe on-state P-channel MIS transistor is Tox2 in thickness so that gatetunnel current It1 can be sufficiently suppressed. In N-channel MIStransistor NQ1, off-leak current Ioff1 flows. MIS transistor NQ1 is off,and the gate tunnel current thereof is sufficiently small. In thestandby cycle, MIS transistor NQ2 receives a signal at H-level on itsgate, and is turned on. However, its gate insulating film has largethickness Tox2, and gate tunnel current It2 in MIS transistor NQ2 can besufficiently suppressed. In this case, an off-leak current Ioff2 merelyflows through MIS transistor PQ2.

By increasing the thickness of the gate insulating film of the MIStransistor, which is on in the standby cycle, it is possible to suppresssufficiently the gate tunnel current in the standby state. By takingappropriate measures against the off-leak current, the currentconsumption in the standby state can be sufficiently suppressed.

Upon transition to the active cycle, only MIS transistors NQ1, PQ2, NQ3and PQ4 having thin gate insulating films turn from the off state to theon state, and this transition from the on state to the off state isperformed fast owing to small thickness Tox1 of their gate insulatingfilms and small absolute values of their threshold voltages. Inaccordance with the change of input signal IN, the state of the outputsignal can be rapidly driven to a definite state, and any problem suchas increase in access time does not occur. In the standby state, theoutput signal of each CMOS inverter circuit is in the definite state,and such a situation can be prevented that the power supply node and theground node of each CMOS circuit are electrically floated so that theoutput signal of each CMOS circuit is at an uncertain level, and theoutput signal enters the indefinite logical state upon transition to theactive cycle.

Third Embodiment

FIG. 5 shows a structure of a semiconductor device according to a thirdembodiment of the present invention. In FIG. 5, four CMOS invertercircuits are arranged. Back gates of P-channel MIS transistors PQ1-PQ4of these CMOS inverter circuits are commonly connected to an N-well 5,and sources thereof are commonly connected to power supply node 1. Eachof N-channel MIS transistors NQ1-NQ4 has a source connected to groundnode 2 and a back gate coupled to a P-well 6. A well voltage VWN onN-well 5 and a well voltage VWP on P-well 6 change with the operationcycle.

FIG. 6 is a signal waveform diagram representing an operation of thesemiconductor device shown in FIG. 5. In the standby state, as shown inFIG. 6, the voltage VWN applied to N-well 5 is set to a high voltage Vpplevel, and the voltage VWP applied to P-well 6 is set to a negativevoltage VBB level. In the active cycle, the voltage VWN applied toN-well 5 is at power supply voltage VCC level, and the voltage VWPapplied to P-well 6 is at ground potential GND level.

Generally, when the back gate bias becomes deeper in an MIS transistor,the depletion layer in this substrate region expands, and the absolutevalue of the threshold voltage increases. When the depletion layerexpands, the electric field applied to the gate insulating film becomeslow because the capacitance value of the gate insulating filmequivalently increases, and thereby the electric field applied to thegate insulating film becomes weak so that the gate tunnel current can besuppressed. The bias voltages of increased absolute values are appliedto N- and P-wells 5 and 6 in the standby state, to increase the absolutevalues of the threshold voltages of MIS transistors PQ1-PQ4 and NQ1-NQ4,so that the sub-threshold leak currents (off-leak currents) of thesetransistors can be suppressed. Accordingly, both the suppression of thegate tunnel current and the suppression of the off-leak current can beachieved so that the current consumption in the standby state can besignificantly reduced.

In the structure shown in FIG. 5, the CMOS inverter circuits aredirectly coupled to power supply node 1 and ground node 2, the logicallevels of the respective output signal are in the fixed state, andoutput signal OUT can be changed fast in accordance with change involtage level of input signal IN upon transition to the active cycle. Inthe standby state, the back gate biases (substrate biases) of MIStransistors PQ1-PQ4 and NQ1-NQ4 are deepened commonly, and the gatetunnel currents and the off-leak currents can be both reduced regardlessof the logical level of the input signal IN in the standby state.

FIG. 7 schematically shows a structure of the CMOS inverter circuitshown in FIG. 5. In FIG. 7, MIS transistors PQ and NQ of the CMOSinverter circuit are formed respectively in N-well 11 and N-well 12,which are spaced from each other and are formed at a surface of a P-typesemiconductor substrate 10. N-well 12 receives power supply voltage Vccvia an N-type impurity region 12 a. A P-well 13 is formed at the surfaceof N-well 12. P-well 13 serves as a substrate region of N-channel MIStransistor NQ.

P-type impurity regions 11 a and 11 b are formed at the surface ofN-well 11 with a space laid therebetween, and a gate electrode 11 c isformed between impurity regions 11 a and 11 b with a gate insulatingfilm (not shown) underlaid. The gate insulating film under a gateelectrode 11 c has a thickness, which provides a tunnel barrier similarto or smaller than the gate tunnel barrier provided by a silicon oxidefilm of 3 nm in thickness. Unless otherwise specified in the followingdescription, the thin gate insulating film of the MIS transistor hasthickness Tox1, which provides a gate tunnel barrier similar to smallerthan the gate tunnel barrier provided by the silicon oxide film of 3 nmin thickness.

Impurity regions 11 a and 11 b formed in N-well 11 as well as gateelectrode 11 c form P-channel MIS transistor PQ.

An N-type impurity region 11 d is formed at the surface of N-well 11.Through N-type impurity region 11 d, an N-well bias circuit 15 applieswell bias voltage VWN to N-well 11.

N-type impurity regions 13 a and 13 b are formed at the surface ofP-well 13 with a space laid therebetween. A gate electrode 13 c isformed on the channel region between N-type impurity regions 13 a and 13b with a thin gate insulating film underlaid. P-well 13, N-type impurityregions 13 a and 13 b, and gate electrode 13 c form N-channel MIStransistor NQ. A P-type impurity region 13 d is formed at the surface ofP-well 13. P-type impurity region 13 d receives well bias voltage VWPfrom P-well bias circuit 20, and applies the received well bias voltageVWP to P-well 13.

Impurity regions 11 b and 13 b are coupled to an output node generatingan output signal OUTa, and impurity regions 11 a and 13 a are suppliedwith power supply voltage Vcc and ground voltage Vss (=GND). Gateelectrodes 11 c and 13 c commonly receive an input signal INa.

The bias voltages of N- and P-wells 11 and 13 are switched depending onthe standby cycle and the active cycle. In the standby cycle, N-well 11is set to high voltage Vpp level, a PN junction between N-well 11 andimpurity regions 11 a and 11 b attains a deep reverse bias state, andthe depletion layer expands in N-well 11. Likewise, by applying negativevoltage VBB to P-well 13 in the standby state, a PN junction betweenP-well 13 and N-type impurity regions 13 a and 13 b attains a deepreverse bias state, and the depletion layer expands in P-well 13.

FIG. 8A schematically shows a distribution of a depletion layer DP inthe MIS transistor. In FIG. 8A, depletion layer DP is formed at thevicinities of source region SR and drain region DR even if an inversionlayer is formed in the channel region at the surface of substrate region(well) SUB. This depletion layer, which is a layer containing nocarrier, functions in a similar manner as an insulating layer, and adepletion layer capacitance Cd is formed at the surface of substrateregion SUB. Therefore, depletion layer capacitance Cd is connected inseries to a gate insulating film capacitance Cg provided by a gateinsulating film located between a gate electrode GT and substrate regionSUB. Accordingly, gate insulating film capacitance Cg and depletionlayer capacitance Cd are connected in series as shown in FIG. 8B, gatevoltage Vg and substrate voltage Vsub are capacitance-divided by thesecapacitances Cg and Cd, the electric field applied to the gateinsulating film is weakened, and consequently the gate tunnel barrierequivalently becomes high. Therefore, by providing a deep well bias inthe standby state, the thickness of gate insulating film is equivalentlyincreased, and the height of gate tunnel barrier is increased.

Although a gate tunnel current flows between gate electrode GT and drainregion DR, their facing area is small, and this gate tunnel current issufficiently smaller than the gate tunnel current flowing from/to thechannel region. Thereby, the gate tunnel current can be reliablysuppressed.

FIG. 9 schematically shows a structure of N-well bias circuit 15 shownin FIG. 7. In FIG. 9, N-well bias circuit 15 includes a Vpp generatingcircuit 15 a for generating high voltage Vpp, a level shifter 15 b forshifting a voltage level of an internal operation instructing signalφACT instructing the internal operation cycle, and a multiplexer (MUX)15 c for selecting one of high voltage Vpp generated by VPP generatingcircuit 15 a and power supply voltage Vcc in accordance with a switchingcontrol signal φMXN received from level shifter 15 b, to generate N-wellbias voltage VWN. Internal operation instructing signal φACT changesbetween power supply voltage Vcc and ground voltage GND (=Vss). Levelshifter 15 b converts internal operation instructing signal φACT of anamplitude of power supply voltage Vcc into switching control signal φMXNof an amplitude of high voltage Vpp. Multiplexer 15 c can reliablyselects one of power supply voltage Vcc and high voltage Vpp to generateN-well bias voltage VWN in response to switching control signal φ MXN.

Vpp generating circuit 15 a for generating high voltage Vpp is formed ofa general circuit that utilizes a charge pump operation of a capacitor.Level shifter 15 b is formed of a circuit utilizing, e.g., an ordinarylevel converter circuit of a latch type. Multiplexer 15 c is formedutilizing an ordinary transmission gate, for example.

A relationship in logical level between internal operation instructingsignal φACT and switching control signal φMXN is appropriatelydetermined in accordance with the logical levels, at which internaloperation instructing signal φACT attains in the standby state and theactive state, respectively.

FIG. 10 schematically shows a structure of P-well bias circuit 20 shownin FIG. 7. In FIG. 10, P-well bias circuit 20 includes a VBB generatingcircuit 20 a for generating negative voltage VBB, a level shifter 20 bfor shifting the level of internal operation instructing signal φACT,and a multiplexer (MUX) 20 c for selecting one of ground voltage GND andnegative voltage VBB in accordance with switching control signal φMXPreceived from level shifter 20 b, to produce P-well bias voltage VWP.

Level shifter 20 b converts internal operation instructing signal φACTchanging between power supply voltage Vcc and ground voltage GND intoswitching control signal φMXP changing between power supply voltage Vccand negative voltage VBB. The relationship in logical level betweeninternal operation instructing signal φACT and switching control signalφMXN is appropriately determined in accordance with the logical level ofinternal operation instructing signal φACT in the standby state as wellas the structure of multiplexer 20 c. In the standby state, multiplexer20 c selects negative voltage VBB generated from VBB generating circuit20 a in accordance with switching control signal φMXP. In the activecycle, multiplexer 20 c selects ground voltage GND in accordance withswitching control signal φMXP.

VBB generating circuit 20 a is formed of a charge pump circuit utilizinga charge pump operation of a capacitor. Level shifter 20 b is formed of,e.g., a level converter circuit of a latch type.

In the structure shown in FIG. 5, both the voltages of P- and N-wells 6and 5 vary in accordance with the operation cycle. However, the biasvoltage of only one of P- and N-wells 6 and 5 may be switched inaccordance with the operation cycle.

Only the MIS transistor, which is on in the standby state, may beadapted to be deepened in substrate bias.

[First Modification]

FIG. 11 schematically shows a structure of a first modification of thethird embodiment of the present invention. In FIG. 11, four CMOSinverter circuits are arranged. These CMOS inverter circuits includesrespective P-channel MIS transistors PQ1-PQ4 and respective N-channelMIS transistors NQ1-NQ4. MIS transistors PQ1-PQ4 have sources connectedto a power supply line 21. MIS transistors NQ1-NQ4 have sourcesconnected to a ground line 23. Power supply line 21 and ground line 23are coupled to power supply switching circuits 22 and 24, respectively.Power supply switching circuits 22 and 24 change the voltage levels ofvoltages PV and NV on power supply line 21 and ground line 23,respectively, in accordance with internal operation instructing signalφACT.

FIG. 12 is a signal waveform diagram representing an operation of thesemiconductor device shown in FIG. 11. The operation of thesemiconductor device shown in FIG. 11 will now be described, referringto FIG. 12

In the standby state, power supply switching circuit 22 transmits groundvoltage GND as the voltage PV onto power supply line 21, and powersupply switching circuit 24 transmits power supply voltage Vcc as thevoltage NV onto ground line 23. MIS transistors PQ1-PQ4 receive groundvoltage GND on their respective sources, and are made off independentlyof the respective gate voltages. MIS transistors NQ1-NQ4 receive powersupply voltage Vcc on the respective sources, and are made offindependently of the voltage levels on the respective gates.Accordingly, a gate tunnel current hardly occurs in MIS transistorsPQ1-PQ4 and NQ1-NQ4 regardless of the logical level of input signal IN.

When the active cycle starts, power supply switching circuit 22transmits power supply voltage Vcc as the voltage PV onto power supplyline 21, and power supply switching circuit 24 transmits ground voltageGND as the voltage NV onto ground line 23. In this state, MIStransistors PQ1-PQ4 and NQ1-NQ4 operate as the CMOS inverter circuitseach receiving power supply voltage Vcc and ground voltage GND as theoperation power supply voltages, and produces output signal OUT inaccordance with input signal IN. All MIS transistors PQ1-PQ4 and NQ1-NQ4each have a gate insulating film of a small thickness Tox1, and canoperate fast.

In the structure shown in FIG. 11, MIS transistors PQ1-PQ4 receive, asthe source voltage, the ground voltage in the standby state. Thereby,the depletion layers in the substrate regions of MIS transistors PQ1-PQ4expand to reduce the electric fields applied to their gate insulatingfilms so that the gate tunnel currents can be suppressed. Accordingly,the gate tunnel current can be reliably suppressed in each of MIStransistors PQ1-PQ4 independently of the logical level of input signalIN in the standby state. As for MIS transistors NQ1-NQ4, when the sourceis at power supply voltage Vcc level, the source to substrate is in thedeep reverse bias state, and the depletion layer expands. Therefore, theelectric fields applied to the gate insulating films of MIS transistorsNQ1-NQ4 can be mitigated, and the gate tunnel current can be suppressed.

In MIS transistors NQ1-NQ4 and PQ1-PQ4, a tunnel current may flowbetween the gate and drain. This tunnel current between the gate anddrain can be suppressed by setting the voltages PV and NV on powersupply line 21 and ground line 23 to be equal to ground voltage GND andpower supply voltage Vcc, respectively, in the standby cycle. Theabsolute values of threshold voltages are also increased in MIStransistors PQ1-PQ4 and NQ1-NQ4, and the off-leak current is alsoreduced so that the current consumption in the standby state can bereduced.

Generally, the bias between the gate and source is merely required to beset to a reverse bias state deeper than the bias state in the normaloperation. Thereby, it is possible to achieve a state equivalent to thestate that the substrate bias is deepened in the normal operation, andthe depletion layer can be expanded, and the absolute value of thethreshold voltage can be also increased. Thereby, the gate tunnelcurrent and the off-leak current both can be reduced.

Power supply switching circuits 22 and 24 are merely required to be ableto transmit either power supply voltage Vcc or ground voltage GND topower supply line 21 and ground line 23, respectively, in accordancewith internal operation instructing signal φACT.

[Second Modification]

FIG. 13 schematically shows a structure of a second modification of thethird embodiment of the present invention. In the structure shown inFIG. 13, a power supply switching circuit 26 for switching the voltagelevel on power supply line 21 in response to internal operationinstructing signal φACT is provided for power supply line 21. A powersupply switching circuit 28 for switching the voltage level on groundline 23 in accordance with internal operation instructing signal φACT isprovided for ground line 23.

Power supply switching circuit 26 transmits a voltage V1 lower thanpower supply voltage Vcc onto power supply line 21 in the standby cycle,and transmits power supply voltage Vcc onto power supply line 21 in theactive cycle (active state). Power switching circuit 28 transmits avoltage V2 onto ground line 23 in the standby cycle (standby state), andtransmits ground voltage GND onto ground line 23 in the active cycle.Structures other than the above are substantially the same as thoseshown in FIG. 11, and the corresponding portions are denoted by the samereference numerals.

In the structure shown in FIG. 13, the voltage V1 is lower than powersupply voltage Vcc, and the voltage V2 is higher than ground voltageGND. These voltages V1 and V2 may be equal in level.

In the structure of the semiconductor device shown in FIG. 13, thevoltage PV on power supply line 21 is the voltage V1 lower than powersupply voltage Vcc, and the voltage VN on ground line 23 is set to avoltage V2 higher than ground voltage GND in the standby state, as shownin a signal waveform diagram of FIG. 14. In the MIS transistor, aneffect similar to the “substrate effect” appears when the source voltagechanges to lower the gate-source voltage. Therefore, the depletion layerexpands in the substrate region (well region) as shown in FIG. 15, andan effect similar to the foregoing effect achieved by changing the wellpotential can be achieved.

Accordingly, even when the voltages V1 and V2 are different in voltagelevel from ground voltage GND and power supply voltage Vcc,respectively, the gate tunnel current can be suppressed by employing thevoltages V1 and V2, which can set the gate-source voltages of MIStransistors PQ1-PQ4 and NQ1-NQ4 to a deeper reverse bias state in thestandby cycle than the bias state thereof achieved in the active cycle.

Accordingly, even if voltages V1 and V2 are equal to, e.g., negative andhigh voltages VBB and VPP, respectively, a similar effect can beachieved. Power switching circuits 26 and 28 may be formed of structuressimilar to those shown in FIGS. 9 and 10 already described, in whichcase appropriate level shifters depending on the polarities and voltagelevels of the voltages V1 and V2 are employed, if necessary.

According to the third embodiment of the present invention, as describedheretofore, the substrate PN junction is set to a deeper reverse biasstate in the standby state than that in the active cycle. In the standbystate, therefore, the depletion layer can be expanded in the well region(substrate region) so that the electric field applied to the gateinsulating film can be mitigated, and the gate tunnel current can besuppressed. Further, the depletion layer capacitance can mitigate theelectric field generated near the drain so that the gate-drain electricfield can be relaxed, and the tunnel current between the gate and draincan be also suppressed.

Further, the depletion layer is expanded in the standby state of the MIStransistor, and the absolute value of the threshold voltage isequivalently increased so that the off-leak current can also be reduced.

By utilizing a so-called LDD (Lightly Doped Drain) structure, the drainelectric field can be relaxed, and the tunnel current between the gateand drain can be suppressed.

In FIG. 15, the source voltage is switched between a voltage of V1/V2and a voltage of Vcc/GND. When the voltages V1 and V2 are applied,depletion layer DP expands in substrate region SUB, because the reversebias of the PN junction between source region SR and substrate regionSUB becomes deep, and depletion layer DP expands in either of thevoltages V1 and V2.

Fourth Embodiment

FIG. 16 schematically shows a structure of a semiconductor deviceaccording to a fourth embodiment of the present invention. For thestructure shown in FIG. 16, an input signal IN is at a predetermined,L-level in the standby cycle. In FIG. 16, four CMOS inverter circuitsare arranged, similarly to the third embodiment. P-channel MIStransistors PQ1 and PQ3 which are on in the standby cycle have backgates (substrate regions) formed in N-well 5 receiving bias voltage VWNfrom N-well bias circuit 15. N-channel MIS transistors NQ2 and NQ4 whichare on in the standby cycle have back gates formed in P-well 6 receivingbias voltage VWP from P-well bias circuit 20.

MIS transistors PQ2, PQ4, NQ1 and NQ3 which are off in the standby cyclehave back gates connected to respective sources. More specifically, theback gates of MIS transistors PQ2 and PQ4 are connected to power supplynode 1, and the sources of MIS transistors NQ1 and NQ3 are connected toground node 2. N- and P-well bias circuits 15 and 20 have structuressimilar to those shown in FIGS. 9 and 10. MIS transistors PQ1-PQ4 andNQ1-NQ4 have gate insulating films which are sufficiently small inthickness (Tox1).

An operation of the semiconductor device shown in FIG. 16 will now bedescribed with reference to a signal waveform diagram of FIG. 17.

In the standby cycle or standby state, input signal IN is at the groundvoltage level, or at L-level, and well bias voltage VWN to N-well 5 isset to high voltage Vpp level. Well bias voltage VWP to P-well 6 is setto negative voltage VBB. Even when P-channel MIS transistors PQ1 and PQ3receive the signals at L-level on their gates, well bias voltage VWN isat high voltage Vpp level, and the depletion layers in the channelregions of MIS transistors PQ1 and PQ3 expand into the substrate region(N-well region) so that the gate tunnel current is sufficientlysuppressed. In N-channel MIS transistors NQ2 and NQ4, well bias voltageVWP of P-well 6 is at negative voltage VBB level, and the depletionlayers expand in the channel regions of MIS transistors NQ2 and NQ4,respectively, so that the gate tunnel current does not occur.

In the active state, well bias voltage VWN on N-well 5 is set to powersupply voltage Vcc level, and well bias voltage VWP of P-well 6 is setto ground voltage GND level. Therefore, MIS transistors PQ1-PQ4 receivethe same back gate bias, and operate under the same operation condition.Also, MIS transistors NQ1-NQ4 receive the same back gate bias, andoperate fast under the same operation condition in the active period. Inthe active state, therefore, output signal OUT can be produced fast inaccordance with input signal IN.

In the structure shown in FIG. 16, each of N-well bias circuit 15 andP-well bias circuit 20 drives the well regions of MIS transistors, whichare half in number as compared to the structure shown in FIG. 5.Accordingly, the area of the well regions to be driven is reduced tohalf so that the loads driven by N- and P-well bias circuits 15 and 20are reduced, and thereby the current consumption is reduced.

[First Modification]

FIG. 18 schematically shows a structure of a first modification of afourth embodiment of the present invention. In FIG. 18, input signal INis at L-level in the standby state. The sources of MIS transistors PQ1and PQ3 kept on in the standby state are coupled to power supply line21, and the sources of MIS transistors PQ2 and PQ4 made off in thestandby cycle are coupled to power supply node 1.

Likewise, the sources of MIS transistors NQ2 and NQ4 kept on in thestandby state are connected to ground line 23. The sources of MIStransistors NQ1 and NQ3 made off in the standby are connected to groundnode 2. Power supply line 21 is supplied with a voltage PV from powersupply switching circuit 26 (or 22), and ground line 23 is supplied witha voltage VN from power supply switching circuit 28 (or 24). Powersupply switching circuit 26 applies the voltage V1 (or ground voltageGND) onto power supply line 21 in the standby cycle. Power supplyswitching circuit 28 applies the voltage V2 (or power supply voltageVcc) onto ground line 23 in the standby cycle. In the active cycle,power supply switching circuit 26 (or 22) applies power supply voltageVcc as the voltage PV, and power supply switching circuit 28 (or 24)applies ground voltage GND onto ground line 23 as the voltage NV. Thestructures of power supply switching circuits 26 (or 22) and 28 (or 24)are the same as those shown in FIGS. 13 and 11. MIS transistors PQ1-PQ4and NQ1-NQ4 each have a gate insulating film of the thickness Tox1.

In the structure shown in FIG. 18, in the standby cycle, MIS transistorsPQ1 and PQ3, which are on in this standby cycle, receive, on theirgates, the voltage (ground voltage or voltage V1) lower than powersupply voltage Vcc which is applied in the active cycle. Therefore, MIStransistors PQ1 and PQ3 are off (and the depletion layers expands) sothat the gate tunnel current is suppressed. MIS transistors NQ2 and NQ4are likewise supplied, on their gates, with the power supply voltage orthe voltage V2, and are off (and the depletion layer expands).Therefore, the gate tunnel currents can be sufficiently suppressed inMIS transistors NQ2 and NQ4.

In the active cycle, power supply switching circuit 26 (or 22) suppliespower supply voltage Vcc as the voltage PV onto power supply line 21,and power supply switching circuit 28 (or 24) transmits ground voltageGND as the voltage NV onto ground line 23. In this state, therefore, MIStransistors PQ1-PQ4 and NQ1-NQ4 operate under the same condition, andchange output signal OUT at high speed in accordance with input signalIN.

In FIG. 18, input signal IN in the standby cycle is at a predetermined,logical level. In this case, the MIS transistor to be on has the sourcebias deepened, and is set into the off state, whereby the gate tunnelcurrent can be sufficiently suppressed in the standby state.

Fifth Embodiment

FIG. 19 schematically shows a structure of a semiconductor deviceaccording to a fifth embodiment of the present invention. In FIG. 19, amain power supply line 30 receiving power supply voltage Vcc isconnected to a sub-power supply line 32 via a switching transistor SWa.In response to control clock signal φ, switching transistor SWa is offin the standby cycle, and is on in the active cycle. A main ground line34 receiving ground voltage GND (Vss) is arranged and connected tosub-ground line 36 via a switching transistor SWb. In response tocontrol clock signal /φ, switching transistor SWb is off in the standbycycle, and is on in the active cycle, similarly to switching transistorSWa.

For the hierarchical power supply structure of the main/sub-power supplylines and main/sub-ground lines, CMOS inverter circuits forming alogical circuit are arranged. Input signal IN is fixed at logicalL-level in the standby state. Input signal IN is received by CMOSinverter circuits of four stages, for example. These CMOS invertercircuits include P-channel MIS transistors Pqa-PQd and N-channel MIStransistors NQa-NQd. MIS transistors PQa and PQc, which are on in thestandby state, each have a gate insulating film of a large thickness ofTox2, and have sources connected to main power supply line 30. MIStransistors PQb and PQd, which are off in the standby state, each have agate insulating film of a small thickness of Tox1, and have sourcescommonly connected to sub-power supply line 32.

Likewise, MIS transistors NQb and NQd, which are on in the standbystate, each have a gate insulating film of a thickness of Tox2, and havesources commonly connected to main ground line 34. MIS transistors NQaand NQc, which are off in the standby state, each have a gate insulatingfilm of a thickness of Tox1, and have sources commonly connected tosub-ground line 36.

Thickness Tox2 is greater than thickness Tox1. Therefore, MIStransistors PQa and PQc have higher gate tunnel barriers than MIStransistors PQb and PQd, and MIS transistors NQb and NQd have highergate tunnel barriers than MIS transistors NQa and NQc. An operation ofthe semiconductor device shown in FIG. 19 will now be described withreference to a signal waveform diagram of FIG. 20.

In the standby state (cycle), input signal IN is at L-level, controlclock signal φ is at H-level (power supply voltage Vcc level), andcontrol clock signal /φ is at ground voltage GND level or L-level.Accordingly, switching transistors SWa and SWb are off, main powersupply line 30 is isolated from sub-power supply line 32, and sub-groundline 36 is isolated from main ground line 34. In this state, off-leakcurrent Ioff flows from main power supply line 30 to sub-power supplyline 32 via switching transistor SWa, and off-leak current Ioff flowsfrom sub-ground line 36 to main ground line 34 via switching transistorSWb. In the CMOS inverter circuits, MIS transistors PQa, PQc, NQb andNQd are on. However, these MIS transistors PQa, PQc, NQb and NQd in theon state have the gate insulating films of Tox2 in thickness, so thatthe gate tunnel current is sufficiently suppressed. Although MIStransistors PQb, PQd, NQa and NQc in the off state have the gateinsulating films of Tox1 in thickness, these transistors are in the off(accumulated) state, and the gate tunnel currents hardly flow.

In these MIS transistors PQb, PQd, NQa and NQc, the off-leak currentsflow between the drains and the sources, respectively.

However, these off-leak currents are suppressed by the switchingtransistors SWa and SWb, and a power supply voltage Vccs on sub-powersupply line 32 is slightly lower than power supply voltage Vcc becauseof the off-leak current and the slight gate tunnel current. Meanwhile,the voltage Vsss on sub-ground line 36 is higher than voltage GND owingto the off-leak current and the gate tunnel current. These voltages Vccsand Vsss are stabilized at the voltage levels, at which a balance isestablished between the off-leak current flow and the gate tunnelcurrent flow that are caused through switching transistors SWa and SWbas well as MIS transistors PQa-PQd and NQa-NQd.

Accordingly, the voltage Vccs on sub-power supply line 32 is lower thanpower supply voltage Vcc, and the voltage Vsss on sub-power supply line36 is higher than ground voltage GND. Thereby, MIS transistors PQb, PQd,NQa and NQc which are off in the standby state have their gate-sourcevoltages in the reverse bias state, and the off-leak currents betweenthe sources and drains can be sufficiently suppressed. Accordingly, boththe gate tunnel current and the off-leak current between the source andthe drain can be reliably suppressed, and the current consumption in thestandby state can be sufficiently reduced.

In the structure of semiconductor device shown in FIG. 19, MIStransistors PQa, PQc, NQb and NQd, which are on in the standby state(cycle) and have thick gate insulating films, have sources connected tomain power supply line 30 and main ground line 34. The output voltagelevels of the respective CMOS inverter circuits are fixed to powersupply voltage Vcc level or ground voltage GND level, and the uncertainstate of the output signals does not occur. In transition from thestandby state to the active state, the MIS transistors having the thingate insulating films can rapidly drive the output signal OUT to thedefinite state in accordance with the change in input signal IN withoutcausing a logically unstable state.

In this transition to the active cycle, switching transistors SWa andSWb are on, and their large current driving capabilities are utilized tosupply the current from main power supply line 30 to sub-power supplyline 32 so that the voltage Vccs can be returned fast to power supplyvoltage Vcc level, while coupling main ground line 34 to sub-ground line36 to return the voltage Vsss rapidly to ground voltage GND level.Thereby, fast operation can be performed in the active cycle to driveoutput signal OUT to the definite state in accordance with the change ininput signal IN.

Switching transistors SWa and SWb are increased in absolute value ofthreshold voltages as well as in the gate tunnel barrier height, inorder that the off-leak currents and the gate tunnel currents can bereduced as much as possible in the off state. However, the currentdriving capability in the on state is sufficiently increased for fastdriving of the CMOS inverter circuits.

FIGS. 21A-21C show, by way of example, the structures of switchingtransistors SWa and SWb. In FIG. 21A, the channel impurity doping isperformed to a high impurity concentration, and the impurityconcentration of the channel region between a source region S and adrain region D. is increased so as to increase absolute value Vth of thethreshold voltage

In the structure of switching transistor SW (SWa, SWb) shown in FIG.21B, the insulating film under a gate G has a large thickness Tox3. Gateinsulating film thickness Tox3 is greater than thickness Tox2. Thereby,switching transistors SWa and SWb each can have the threshold voltage ofa large absolute value and an increased gate tunnel barrier height.

As shown in FIG. 21C, a bias voltage Vbias applied to a substrate region(well region) is deeper than those of other MIS transistors. Also, thethreshold voltage is increased in absolute value, and gate tunnelbarrier is increased in height. Any one of these structures shown inFIGS. 21A-21C may be used. It is merely required that switchingtransistors SWa and SWb have the threshold voltages of an increasedabsolute value Vth, to suppress the off-leak current and the gate tunnelcurrent therethrough.

Upon transition from the standby cycle to the active cycle, the MIStransistor having the thin gate insulating film rapidly transits fromthe off state to the on state, and thereby changes the output signal ofan associated CMOS inverter circuit. Therefore, problems such asincrease in access time in a dynamic type semiconductor memory device(e.g., DRAM) do not occur.

According to a fifth embodiment of the present invention, as describedabove, a hierarchical power supply structure is utilized, and the MIStransistor which is on in the standby state has a gate insulating filmsof a large thickness, and has a source thereof connected to the mainpower supply line or the main ground line. The MIS transistor which isoff in the standby state (standby cycle) has a gate insulating film of asmall thickness, and has a source thereof connected to the sub-powersupply line or the sub-ground line. Thus, the off-leak current and thegate tunnel current in the standby state can be sufficiently suppressed,and the current consumption in the standby state can be reduced.

Upon transition to the active cycle, the MIS transistor having the gateinsulating films of a small thickness transits from the off state to theon state, and the output signal voltage level of an associated circuitis in the fixed state in the standby state. Therefore, the output signalcan be rapidly driven to the definite state without passing through thelogically uncertain state, and the output signal can be rapidly changedin accordance with the input signal, so that the fast operation featurein the active cycle can be sufficiently ensured.

Sixth Embodiment

FIG. 22 schematically shows a structure of a semiconductor deviceaccording to a sixth embodiment of the present invention. Thesemiconductor device shown in FIG. 22 likewise utilizes a hierarchicalpower supply structure, and is provided with main power supply line 30,sub-power supply line 32, sub-ground line 36 and main ground line 34.Using the voltages on these hierarchical power supplies as the operationpower supply voltages, a logic circuit 40 effects predeterminedprocessing on input signal IN to produce output signal OUT.

Input signal IN is at L-level in the standby state. In logic circuit 40,therefore, MIS transistors PQa and PQc which are on in the standby statehave the gate insulating films of a large thickness (Tox2), and have thesources connected to main power supply line 30, similarly to thestructure shown in FIG. 19.

MIS transistors NQb and NQd are thick in gate insulating film, and havethe sources connected to main ground line 34. MIS transistors PQb andPQd as well as NQa and NQc, which enter the off state and may causeoff-leak currents during the standby period, have gate insulating filmsof small thickness Tox1 corresponding to the thickness of 3 nm of thesilicon oxide film, in order to ensure the fast operation feature ofthese transistors. MIS transistors PQb and PQd have the sourcesconnected to sub-power supply line 32, and MIS transistors NQa and NQchave the sources connected to sub-ground line 36.

Sub-power supply line 32 is connected to main power supply line 30 viaswitching transistor SWa, and sub-ground line 36 is connected to mainground line 34 via switching transistor SWb. These structures are thesame as those shown in FIG. 19. The semiconductor device shown in FIG.22 is further provided with a voltage adjusting circuit 42. Voltageadjusting circuit 42 includes replica circuits of logic circuit 40 andswitching transistors SWa and SWb, and drives the voltage levels ofsub-power supply line 32 and sub-ground line 36 to predetermined levelsin accordance with control clock signals φ and /φ in a standby state.

Voltage adjusting circuit 42, of which structure will be describedlater, produces the voltages corresponding to the voltages in theequilibrium state of sub-power supply line 32 and sub-ground line 36 inthe standby state, and rapidly drives the voltage levels of sub-powersupply line 32 and sub-ground line 36 to the stable state upontransition to the standby state. Upon transition to the active cycle,therefore, the voltage levels of sub-power supply line 32 and sub-groundline 36 is prevented from entering an unstable state, which may becaused due to an insufficient period of an active cycle. Thus, theinternal operation can be quickly started after start of the activecycle.

As shown in FIG. 23, in the active cycle, both switching transistors SWaand SWb are on so that the voltage Vccs on sub-power supply line 32 isat the level of power supply voltage Vcc, and the voltage Vsss onsub-ground line 36 is at the level of ground voltage Vss.

In FIG. 23, upon entry into the standby cycle at time t0, both switchingtransistors SWa and SWb are turned off, and off-leak currents flowthrough switching transistors SWa and SWb. In logic circuit 40, thecurrent on sub-power supply line 32 is consumed due to the off-leakcurrents (and tunnel leak currents) of MIS transistors PQb and PQd.Therefore, voltage Vccs on sub-power supply line 32 slowly changes tothe voltage level, which keeps balance between the leak current(off-leak current and gate tunnel current) supplied by switchingtransistor SWa and the leak currents flowing through these MIStransistors PQb and PQd. On sub-ground line 36, voltage Vsss likewiseattains the voltage level, at which the leak currents flowing throughMIS transistors NQa and NQc is balanced with the leak current flowingthrough switching transistor SWb. Transition of voltages Vccs and Vsssto equilibrium voltages Vce and Vse require a long time because thetransition is caused by the leak currents, and voltages Vccs and Vsssattain equilibrium voltages Vce and Vse at time t1, respectively.

In transition from the standby cycle to the active cycle, switchingtransistors SWa and SWb having relatively large current drivecapabilities recover the voltages on sub-power supply line 32 andsub-ground line 36 to power supply voltage Vcc and ground voltage Vss,respectively. However, when the active cycle starts again before time t1after entering the standby cycle, the voltage Vccs and Vsss on sub-powersupply line 32 and sub-ground line 36 in transition to the active cycleare at the voltage levels in the transient state, and the startingvoltage levels thereof upon transition to the active cycle aredifferent. Therefore, the times required for recovery of the voltagelevels of the sub-power supply line and the sub-ground line differdepending on the voltage levels of voltages Vccs and Vsss. Accordingly,the time periods required for stabilization of the voltages Vccs andVsss on sub-power supply line 32 and sub-ground line 36 after transitionto the active cycle varies to vary the operation speeds of transistorsof the logic circuit so that a malfunction may occur due to shift ofinternal operation timing.

In view of the above, voltage adjusting circuit 42 always producesequilibrium voltages Vce and Vse as shown in FIG. 22, and forciblydrives the voltages on sub-power supply line 32 and sub-ground line 36to equilibrium voltages Vce and Vse within a short time after transitionto the standby cycle. This reduces a time Tt, which is required forsetting voltages Vccs and Vsss to the equilibrium state after transitionto the standby cycle, and the voltages Vccs and Vsss is set to the equalstarting voltage levels at the time of transition to the active cycle.Thereby, a variation in recovery time of the power supply voltage upontransition to the active cycle can be eliminated so that accurate andstable internal circuit operations can be ensured.

FIG. 24 shows a structure of voltage adjusting circuit 42 shown in FIG.22. In FIG. 24, voltage adjusting circuit 42 includes a replica circuit42 a producing equilibrium voltages Vce and Vse, a differentialamplifier 42 b for differentially amplifying a reference voltage Vref1corresponding to equilibrium voltage Vce and supplied from replicacircuit 42 a and a voltage on a node 42 h, a differential amplifier 42 cfor differentially amplifying a reference voltage Vref2 corresponding toequilibrium voltage Vse and supplied from replica circuit 42 a and avoltage on a node 42 i, a transmission gate 42 d made conductive in thestandby cycle in response to control clock signals φ and /φ, to transmitthe voltage on node 42 h onto sub-power supply line 32, and atransmission gate 42 e made conductive in a same phase as transmissiongate 42 d in response to control clock signals φ and /φ, to transmit thevoltage on node 42 i onto sub-ground line 36.

Differential amplifier 42 b differentially amplifies reference voltageVref1 on output node 42 f of replica circuit 42 a and the voltage onnode 42 h, and transmits the result of differential amplification tonode 42 h. Accordingly, equilibrium voltage Vce at the same voltagelevel as reference voltage Vref1 is produced on node 42 h.

Likewise, differential amplifier 42 c differentially amplifies referencevoltage Vref2 on output node 42 g of replica circuit 42 a and thevoltage on node 42 i, and transmits the result of differentialamplification to node 42 i. Accordingly, the voltage on node 42 iattains the same voltage level as reference voltage Vref2, andequilibrium voltage Vse is produced on node 42 i.

Replica circuit 42 a includes: a P-channel MIS transistor SW1 r which isconnected between power supply node 1 and node 42 f, and has a gateconnected to power supply node 1; an N-channel MIS transistor SW2 rwhich is connected between a node 42 g and ground node 2, and has a gateconnected to ground node 2; P- and N-channel MIS transistors RP1 and RN1which are connected in series between power supply node 1 and node 42 gand each have a gate connected to ground node 2; and P- and N-channelMIS transistors RP2 and RN2 which are connected in series between node42 f and ground node 2, and have gates connected to drains of MIStransistors RP1 and RN1, respectively. MIS transistors RP1 and RN2 eachhave a gate insulating film of the large thickness of Tox2. MIStransistors RN1 and RP2 each have a gate insulating film of thethickness of Tox1.

Replica circuit 42 a is a replica of logic circuit 40 and switchingtransistors SWa and SWb shown in FIG. 22. More specifically, MIStransistor RP1 represents MIS transistors PQa and PQc shown in FIG. 22,and MIS transistor RP2 represents MIS transistors PQb and PQd connectedto sub-power supply line 32 shown in FIG. 22. MIS transistor RN1represents MIS transistors NQa and NQc shown in FIG. 22, and MIStransistor RN2 represents MIS transistors NQb and NQd shown in FIG. 22.MIS transistors SW1 r and SW2 r represent switching transistors SWa andSWb shown in FIG. 22, respectively.

In replica circuit 42 a and logic circuit 40 shown in FIG. 22, MIStransistors SW1 r and RP2 have a size (ratio of gate width to gatelength) ratio determined to be equal to a ratio between the size ofswitching transistor SWa and the total size of MIS transistors PQb andPQd. The total size of MIS transistors PQb and PQd corresponds to atotal value of their current drive capabilities, and represents a sum ofthe channel width to the channel length ratios. Likewise, the size ratio(the channel width to channel length ratio) of MIS transistor SW2 r toMIS transistor RN1 is set to be equal to the ratio of the size ofswitching transistor SWb to the total size (i.e., total current drivepower and, in other words, the sum of the channel width to channellength ratios) of MIS transistors NQa and NQc. MIS transistors RP1 andRP2 correspond to the structures formed by reducing the total size ofMIS transistors PQa and PQc with the ratio of replica circuit 42 a,respectively. MIS transistor RN2 corresponds to the structure formed byscaling down the total size of MIS transistors NQb and NQd shown in FIG.22.

In replica circuit 42 a, sizes of respective components are determinedso as to simulate the flow of current on sub-power supply line 32 andsub-ground line 36 in the standby state. Based on the sizes thusdetermined, the components are reduced at a certain proportionalreduction ratio, or a scaling rate. In the standby cycle, input signalIN (see FIG. 22) is at L-level, and therefore, replica circuit 24 a inFIG. 24 simulates the standby current flowing through logic circuit 40as well as the voltages on sub-power supply line 32 and sub-ground line36 in the standby cycle.

In replica circuit 42 a, voltage Vref1 on node 42 f is determined by asum of an off-leak current Ioffc supplied from MIS transistor SW1 r anda gate tunnel current flowing between the gate and drain of MIStransistor SW1 r as well as off-leak current Ioff1 flowing through MIStransistor RP2 and a gate tunnel current. The gate tunnel currentbetween the gate and drain of MIS transistor SW1 r is much smaller thanoff-leak current Ioffc because MIS transistor SW1 r is off. Therefore,voltage Vref1 on node 42 f is approximately at the voltage level, atwhich off-leak current Ioffc of MIS transistor SW1 r is balanced withoff-leak current Ioff1 of MIS transistor RP2. More specifically, thevoltage level of reference voltage Vref1 is equal to such a voltagelevel of voltage Vccs that a sum of the off-leak currents flowingthrough MIS transistors PQb and PQd of logic circuit 40 in FIG. 22 isbalanced with the off-leak current flowing through switching transistorSWa.

Likewise, reference voltage Vref2 is kept at such a voltage level thatoff-leak currents Ioff2 and Ioffs of MIS transistors RN1 and SW2 r arebalanced with each other with the gate tunnel current of MIS transistorSW2 r ignored. Off-leak currents Ioff2 and Ioffs are equivalent to theoff-leak currents flowing through MIS transistors NQa and NQc shown inFIG. 22 and the off-leak current flowing through switching transistorSWb, respectively. Therefore, reference voltage Vref2 is at the voltagelevel where the voltage Vsss on sub-ground line 36 is kept in anequilibrium state in the standby cycle.

Differential amplifiers 42 b and 42 c receive reference voltages Vref1and Vref2, and produce equilibrium voltages Vce and Vse, which are equalto reference voltages Vref1 and Vref2, respectively, on internal nodes42 h and 42 i. In the standby cycle, transmission gates 42 d and 42 eare on, and therefore sub-power supply line 32 and sub-ground line 36are driven by differential amplifiers 42 b and 42 c, respectively, sothat the voltages on sub-power supply line 32 and sub-ground line 36 arerapidly driven to the voltage levels of equilibrium voltages Vce andVse, respectively.

At the time of transition from the active cycle to the standby cycle,therefore, voltage adjusting circuit 42 can rapidly drive sub-powersupply line 32 and sub-ground line 36 to the voltage levels ofequilibrium voltages Vce and Vse as shown in FIG. 23, respectively. Atthe time of transition from the standby cycle to the active cycle,therefore, it is possible to prevent the voltage levels of sub-powersupply line 32 and sub-ground line 36 from changing from the transientstate, and the internal circuits can operate accurately at a fast timingafter transition to the active cycle.

Voltage adjusting circuit 42 is formed through the same manufacturingprocesses as switching transistors SWa and SWb as well as logic circuit40. Therefore, the voltage adjusting circuit 42 can also monitor thevariation and the temperature-dependent deviation in power supplyvoltage Vcc with respect to the actual circuitry. Regardless of thevariations in operation environment, equilibrium voltages Vce and Vsecan be stably and accurately produced to be transmitted onto sub-powersupply line 32 and sub-ground line 36, respectively.

By utilizing replica circuit 42 a, it is also possible to replicatereliably the influences by the gate tunnel current (current between thegate and drain) flowing through the MIS transistor in the off state aswell as the gate tunnel current flowing through the MIS transistor inthe on state. Therefore, reference voltages Vref1 and Vref2 can beproduced while accurately monitoring the influences by the leak currentsdue to the gate tunnel currents and the off-leak currents.

[First Modification]

FIG. 25A schematically shows a structure of a first modification of thesixth embodiment of the present invention. In FIG. 25A, a plurality ofsub-power supply lines 32-1 to 32-n are provided for main power supplyline 30. These sub-power supply lines 32-1 to 32-n are coupled to mainpower supply line 30 via switching transistors SWC-1 to SWC-n formed ofP-channel MIS transistors, respectively.

For main ground line 34, sub-ground lines 36-1 to 36-n are provided.Sub-ground lines 36-1 to 36-n are coupled to main ground line 34 viaswitching transistors SWS-1 to SWS-n formed of N-channel MIStransistors, respectively. A CMOS logic circuit 40-i is provided forsub-power supply line 32-i and sub-ground line 36-i, with i being any of1, 2, . . . n.

Switching transistors SWC-1 to SWC-n and SWS-1 to SWS-n have sizes(ratios between channel widths and channel lengths), which depend on thesizes of the MIS transistors connected to sub-power supply lines 32-1 to32-n of corresponding CMOS logic circuits 40-1 to 40-n and the sizes ofMIS transistors connected to sub-ground lines 36-1 to 36-n. In each ofCMOS logic circuits 40-1 to 40-n, the MIS transistors are selectivelyconnected to the sub-power supply lines, main power supply lines,sub-ground lines and main ground lines, depending on the logical levelsof the corresponding input signals IN1 to INn in the standby cycle.

The sizes of switching transistors SWC-1 to SWC-n and SWS-1 to SWS-n areadjusted in accordance with the structures of corresponding CMOS logiccircuits 40-1 to 40-n such that voltages Vccs1 to Vccsn on sub-powersupply lines 32-1 to 32-n in the standby cycle becomes equal toequilibrium voltage Vce, and voltages Vss1 to Vssn on sub-ground lines36-1 to 36-n becomes equal to the level of the common equilibriumvoltage Vse in the standby cycle.

In FIG. 25B, the voltages on sub-power supply lines 32-1 to 32-n are atthe equilibrium voltage Vce level and at the level of voltage Vcc in theactive cycle. The voltages Vss1 to Vssn on sub-ground lines 36-1 to 36-nare equal to ground voltage Vss in the active cycle. Upon entry into thestandby cycle, control clock signal φ and complementary control clocksignal /φ attain H- and L-levels, respectively, and switchingtransistors SWC-1 to SWC-n and SWS-1 to SWS-n are turned off. In thisstate, all the voltages on sub-power supply lines 32-1 to 32-n and allthe voltages on sub-ground lines 36-1 to 36-n reach the commonequilibrium voltages Vce and Vse, respectively owing to the gate tunnelcurrents and the off-leak currents.

At the time of transition from the standby cycle to the active cycle,the voltages on sub-power supply lines 32-1 to 32-n and sub-ground lines36-1 to 36-n are all at the same levels, respectively. Even if theseCMOS logic circuits 40-1 to 40 n operate at the same timing in theactive cycle, the recovery time periods of the power supply voltage andground voltage are uniform in CMOS logic circuits 40-1 to 40-n so thatit is possible to prevent a malfunction due to timing mismatch caused byunstable signals.

FIG. 26 shows, by way of example, a structure of CMOS logic circuit 40-i(i=1, 2, . . . , n) shown in FIG. 25A. In FIG. 26, CMOS logic circuit40-i includes P-channel MIS transistors PQ1-PQ4 and N-channel MIStransistors NQ1-NQ4 connected in series to respective MIS transistorsPQ1-PQ4.

In the standby cycle, input signal IN is at L-level, and MIS transistorsPQ1 and PQ3 have sources connected to main power supply line 30. Also,MIS transistors PQ2 and PQ4 have sources connected to sub-power supplyline 32-i. Likewise, MIS transistors NQ1 and NQ3 have sources connectedto sub-ground line 36-i, and MIS transistors NQ2 and NQ4 have sourcesconnected to main ground line 34. MIS transistors NQ1, NQ3, PQ2 and PQ4each have a gate insulating film of the small thickness Tox1, becausethese transistors are off in the standby cycle. MIS transistors PQ1,PQ3, NQ2 and NQ4 which are on in the standby cycle each have a gateinsulating film of the large thickness Tox2.

Switching transistor SWC-i between sub-power supply line 32-i and mainpower supply line 30 has a size (ratio of channel width to channellength) determined such that the off-leak current and gate tunnelcurrent thereof is balanced with the leak current (i.e., a sum of theoff-leak current and gate tunnel current) flowing through MIStransistors PQ2 and PQ4 in the standby cycle. Also, switching transistorSWS-i have a size (ratio of channel width to channel length, W/L)determined such that the leak current flowing through MIS transistorsNQ1 and NQ3 is balanced with the off-leak current and the gate tunnelcurrent thereof.

In the standby cycle, MIS transistors PQ1 and PQ3 are on. However, theyhave the gate insulating films of thickness Tox2, and therefore the gatetunnel currents therein are substantially suppressed. MIS transistorsPQ2 and Q4 having thin gate insulating films are off in the standbycycle, and the off-leak currents flow between the drains and the sourcesas indicated by arrows in FIG. 26, and at the same time, the gate tunnelcurrent flows between the gate and the drain in these MIS transistors.However, MIS transistors PQ2 and PQ4 are off in the standby cycle, andthe gate tunnel currents thereof are extremely small. In MIS transistorsNQ1 and NQ3, the gate tunnel current flows from the drain to the gate,and the off-leak current flows between the drain and source. The gatetunnel currents of MIS transistors NQ1 and NQ3 are small in value, andthese gate tunnel currents hardly affect the current on sub-ground line36-i. Therefore, by adjusting the sizes of switching transistors SWC-iand SWS-i in consideration of only the factors of the off-leak currents,the voltages on sub-power supply line 32-i and sub-ground line 36-1 inthe standby cycle can be set to predetermined voltage levels,respectively. In this size adjustment, a formula for obtaining thesub-threshold current is used to obtain such a size of switchingtransistor SWC-i that a sum of the off-leak currents of MIS transistorsPQ2 and PQ4 is equal to the off-leak current flowing through switchingtransistor SWC-i (and the voltage level of voltage Vccs in the standbycycle reaches the predetermined equilibrium level). The size ofswitching transistor SWS-i is determined similarly to the above.

[Second Modification]

FIG. 27 schematically shows a structure of a second modification of thesixth embodiment of the present invention. In FIG. 27, a voltageadjusting circuit 52 is provided commonly to the power supply system(sub-power supply lines and sub-ground lines) of CMOS logic circuits40-1 to 40-n. CMOS logic circuits 40-1 to 40-n and switching transistorsSWC-1 to SWC-n and SWS-1 to SWS-n have the same structures as thoseshown in FIG. 25A. Therefore, the sizes (ratios of channel widths tochannel lengths) of switching transistors SWC-1 to SWC-n are adjustedsuch that the voltages on sub-power supply lines 32-1 to 32-n are equalto equilibrium voltage Vce in the standby cycle. Also, the sizes ofswitching transistors SWS-1 to SWS-n are adjusted such that the voltageson sub-ground lines 36-1 to 36-n are equal to equilibrium voltage Vse.These structures are the same as those shown in FIG. 25A.

Voltage adjusting circuit 52 is provided commonly to sub-power supplylines 32-1 to 32-n and sub-ground lines 36-1 to 36-n. Voltage adjustingcircuit 52 includes a replica circuit for one CMOS logic circuit andcorresponding switching transistors SWC and SWS, and producesequilibrium voltages Vce and Vse in the standby cycle. Voltage adjustingcircuit 52 has the same structure as that shown in FIG. 24, and producesequilibrium voltages Vce and Vse based on the leak current of thereplica circuit.

Output voltage Vce of voltage adjusting circuit 52 is transmitted tosub-power supply lines 32-1 to 32-n via transfer gates (or transmissiongates) PX-1 to PXn, which are turned on in response to control clocksignal /φ in the standby cycle. Equilibrium voltage Vse produced fromvoltage adjusting circuit 52 is transmitted to sub-ground lines 36-1 to36-n via transfer gates (or transmission gates) NX1 to NXn, which areturned on in response to control clock signal φ in the standby cycle. InFIG. 27, transfer gates PX1 to PXn are represented as P-channel MIStransistors, respectively, and transfer gates NX1 to NXn are representedas N-channel MIS transistors, respectively. These transfer gates PX1 toPXn and NX1 to NXn may be formed of CMOS transmission gates.

Switching transistors SWC-1 to SWC-n have sizes so adjusted as toprovide the equal equilibrium voltages on sub-power supply lines 32-1 to32-n in the standby cycle. Also, switching transistors SWS-1 to SWS-nhave sizes so adjusted as to provide the equal equilibrium voltages onsub-ground lines 36-1 to 36-n in the standby cycle. Therefore, all thevoltages ultimately appearing on sub-power supply lines 32-1 to 32-n andsub-ground lines 36-1 to 36-n in the standby cycle are equal to eachother. In the standby cycle, therefore, equilibrium voltages Vce andVse, which are supplied from the single voltage adjusting circuit 52,are transmitted via transfer gates PX1 to PXn to respective sub-powersupply lines 32-1 to 32-n and to sub-ground lines 36-1 to 36-n viarespective transfer gates NX1-NXn, respectively. Thereby, the voltageson sub-power supply lines 32-1 to 32-n can be rapidly driven toequilibrium voltage Vce level, and the voltages on sub-ground lines 36-1to 36-n are rapidly driven to equilibrium voltage Vse level in thestandby cycle.

Accordingly, upon transition from the standby cycle to the active cycle,all the voltages on these sub-power supply lines 32-1 to 32-n can be atthe equal level, and all the voltages on sub-ground lines 36-1 to 36-ncan be at the equal level. Therefore, it is possible to preventvariation in voltage level on sub-power supply lines 32-1 to 32-n aswell as variation in voltage level on sub-ground lines 36-1 to 36-n,which may be caused depending on the time length of the standby cycle,and the operation power supply voltages of CMOS logic circuits 40-1 to40-n can be stabilized at a faster timing after transition to the activecycle, and the stability of the operations of internal circuits can beensured.

[Third Modification]

FIG. 28 schematically shows a structure of a third modification of thesixth embodiment of the present invention. The structure shown in FIG.28 differs from the structure shown in FIG. 25A in the following points.Transmission gates CTM1, CTM2, . . . , CTMn−1, which are turned on inthe standby cycle in response to control clock signals φ and /φ appliedfrom a control clock signal generating circuit 54, are arranged betweensub-power supply lines 32-1 to 32-n. For sub-ground lines 36-1 to 36-n,transmission gates STM1, STM2, . . . , STMn−1, which are turned on inthe standby cycle in response to control clock signals φ and /φ appliedfrom control clock signal generating circuit 54, are arranged.

In the standby cycle, therefore, these transmission gates CTM1-CTMn−1interconnect sub-power supply lines 32-1 to 32-n together, andtransmission gates STM1 to STMn−1 interconnect sub-ground lines 36-1 to36-n together. Structures other than the above are the substantiallysame as those shown in FIG. 25A. The corresponding portions are allottedwith the same reference numerals, and description thereof is notrepeated.

Control clock signal generating circuit 54 produces control clocksignals φ and /φ in accordance with internal operation instructingsignal φACT. In the standby cycle, the equilibrium voltages on sub-powersupply lines 32-1 to 32-n are at the equal level owing to the adjustmentof the sizes of switching transistors SWC-1 to SWC-n. Also, theequilibrium voltages on sub-ground lines 36-1 to 36-n are at the equallevel in the standby cycle owing to the adjustment of sizes of switchingtransistors SWS-1-SWS-n. In the standby cycle, therefore, transmissiongates CTM1-CTMn−1 interconnect sub-power supply lines 32-1-32-ntogether, and transmission gates STM1-STMn−1 interconnect sub-groundlines 36-1-36-n together, whereby the voltages on sub-power supply lines32-1 to 32-n in the standby cycle can be stably kept at the equalequilibrium voltage level. Likewise, the voltages on sub-ground lines36-1-36-n can be stably kept at equilibrium voltage Vse.

In the standby cycle, the voltages on sub-power supply lines 32-1 to32-n are reliably set to the equal level, and the voltages on sub-groundlines 36-1 to 36-n are reliably set to the equal level. Upon transitionfrom the standby cycle to the active cycle, the voltage recovery timeperiods of respective sub-power supply lines 32-1 to 32-n and sub-groundlines 36-1 to 36-n can be equal to each other. Therefore, CMOS logiccircuits 40-1 to 40-n can start the operation at the same timing in theactive cycle, and the stable and accurate internal operation can bereliably implemented.

The voltages on sub-power supply lines 32-1 to 32-n and sub-ground lines36-1 to 36-n can be rapidly stabilized at the equilibrium voltage level.When this equilibrium voltage is kept, the standby currents (off-leakcurrents and gate tunnel currents) of CMOS logic circuits 40-1 to 40-nare minimized, and the current consumption in a standby cycle can beminimized.

[Fourth Modification]

FIG. 29 schematically shows a structure of a fourth modification of thesixth embodiment of the present invention. The structure shown in FIG.29 differs from the structure shown in FIG. 28 in the following points.Equilibrium voltages Vse and Vce supplied from voltage adjusting circuit52 are transmitted to sub-ground line 36-n and sub-power supply line32-n in the standby cycle, respectively. The sub-ground lines 36-1 to36-n are mutually connected by transmission gates STM1-STMn−1 in thestandby cycle, and sub-power supply lines 32-1 to 32-n are mutuallyconnected by transmission gates CTM1-CTMn−1 in the standby cycle. In thestandby cycle, therefore, equilibrium voltages Vse and Vce supplied fromvoltage adjusting circuit 52 are transmitted onto sub-ground lines andsub-power supply lines, and accordingly the voltages on sub-power supplylines 32-1 to 32-n can be rapidly set to equilibrium voltage Vce, andsub-ground lines 36-1 to 36-n can be rapidly driven to equilibriumvoltage Vse.

Voltage adjusting circuit 52 includes a monitor circuit 52 a including areplica circuit, and transmission gates 52 b and 52 c responsive tocontrol clock signals φ and /φ for transmitting equilibrium voltages Vseand Vce onto sub-ground line 36-n and sub-power supply line 32-n,respectively. Monitor circuit 52 a includes a replica circuit for CMOSlogic circuits 40-1 to 40-n as well as a differential amplifier, and thestructure thereof is similar to that shown in FIG. 24.

By utilizing the structure shown in FIG. 29, it is possible to preventsuch a situation that when the standby period is short, sub-power supplylines 32-1 to 32-n carry the voltages at different levels and sub-groundlines 36-1 to 36-n carry the voltages at different levels. At the timeof transition to the active cycle, the internal circuits can stablystart the operation at a faster timing.

Sub-power supply lines 32-1 to 32-n and sub-ground lines 36-1 to 36-ncan quickly reach their respective equilibrium voltages, and the standbycurrents of CMOS logic circuits 40-1 to 40-n can be rapidly driven tothe minimum value so that the current consumption in the standby cyclecan be reduced.

According to the sixth embodiment, as described above, the voltageadjusting circuit quickly drives the sub-power supply lines andsub-ground lines to the equilibrium voltages in the standby cycle, orsets the equilibrium voltages on the sub-power supply lines andsub-ground lines to the equal voltage level in the standby state. Thus,it is possible to prevent variations in recovery time of the operationpower supply voltage, which may occur depending on the length of thestandby cycle period, at the time of transition to the active cycle, andthe internal circuit can stably and quickly performs an operation aftertransition to the active cycle.

Seventh Embodiment

FIG. 30 schematically shows a cross sectional structure of a CMOSinverter circuit of an SOI (Silicon On Insulator) structure, which isused in a seventh embodiment of the present invention. In FIG. 30, theMIS transistor of the SOI structure is formed at a semiconductor layeron a buried oxide film (insulating film) 61 which in turn is formed atthe surface of silicon (Si) substrate 60. N-type impurity regions 63 aand 63 b are formed on buried oxide film 61 with a space laid betweenthem. A P-type impurity region 65 is formed between N-type impurityregions 63 a and 63 b. A gate electrode 67 is formed on P-type impurityregion 65 with a gate insulating film 69 a underlaid. Impurity regions63 a, 63 b and 65, gate insulating film 69 a and gate electrode 67 forman N-channel MIS transistor. P-type impurity region 65 is called a “bodyregion”, and acts as the substrate region of this N-channel MIStransistor. Body region 65 is supplied with a bias voltage, as will bedescribed later.

Further, P-type impurity regions 64 a and 64 b spaced from each otherare formed on buried oxide film (insulating film) 61, and an N-typeimpurity region 66 is formed between impurity regions 64 a and 64 b. Agate electrode 68 is formed on N-type impurity region 66 with a gateinsulating film 69 b underlaid. An insulating film 62 b for elementisolation, which is formed of, e.g., a silicon oxide film, is arrangedbetween impurity regions 63 b and 64 a. Insulating films 62 a and 62 cfor element isolation, which are formed of, e.g., silicon oxide films,are arranged outside impurity regions 63 a and 64 b, respectively.

Impurity regions 64 a, 64 b and 66, gate insulating film 69 b and gateelectrode 68 form a P-channel MIS transistor. Impurity region 66functions as the substrate region of this P-channel MIS transistor, andis called a “body region”.

The transistor of the SOI structure describe above has a small junctioncapacitance, and does not cause a junction leak current because theburied oxide film (insulating film) is formed, so that fast operationand reduced leak current can be achieved.

In the transistor of the SOI structure described above, however, a gatetunnel current flows if the thickness of each of gate insulating films69 a and 69 b is reduced to, e.g., 3.0 nm.

FIG. 31A schematically shows a planar layout of the N-channel MIStransistor shown in FIG. 30. In FIG. 31, gate electrode 67 has aT-shaped feature, and the impurity regions 63 a and 63 b are isolated bya P-type impurity region formed under the gate electrode 67. A heavilydoped P-type impurity region 70 is faced to N-type impurity regions 63 aand 63 b. Heavily doped p-type impurity region 70 is coupled to P-typeimpurity region 65 of the body region formed under gate electrode 67,and transmits a bias voltage Vbp.

FIG. 31B schematically shows distributions of a depletion layer and aninversion layer in the MIS transistor shown in FIG. 31A. In FIG. 31B,impurity regions 63 a and 63 b serve as a source and a drain,respectively. In this case, the thickness of the inversion layergradually decreases from impurity region 63 a of the source regiontowards impurity region 63 b of the drain region. A depletion layer 72is formed under an inversion layer 71. Depletion layer 72 graduallydecreases in thickness as the distance increases from impurity region 63a to a certain position due to the influence by the voltage applied fromgate electrode 67, and then increases in thickness due to the drainelectric field as approaching impurity region 63 b of the drain. Thebody region in which the depletion layer and the inversion layer issupplied with bias voltage Vbp via impurity region 70. By applying biasvoltage Vbp to the body region, a so-called “substrate floating effect”can be prevented, and an influence by the residual charges can beprevented. In the body region shown in FIG. 31B, depletion layer 72 isformed only in a portion of the body region. The MIS transistor of theSOI structure shown in FIGS. 31A and 31B is called a “MIS transistor ofa partial depletion type”.

FIG. 32 schematically shows another planar layout of the MIS transistorof the SOI structure. In the layout shown in FIG. 32, impurity regions63 a and 63 b are isolated from each other by a P-type impurity regionformed under gate electrode 67. Gate electrode 67 has a gate electrodeportion, which extends horizontally in FIG. 32 and isolates impurityregion 63 a and heavily doped P-type impurity region 73 from each other.A P-type impurity region is formed between impurity regions 73 and 63 aand 63 b. Impurity region 73 is electrically connected to a P-typeimpurity region, which is formed under gate electrode 67 having alateral T-shaped figure, and transmits a bias voltage Vbp to the bodyregion. Even in the arrangement shown in FIG. 32, bias voltage Vbp canbe transmitted to the body region. In this structure shown in FIG. 32,the MIS transistor of the partial depletion type is likewiseimplemented.

A planar layout of the P-channel MIS transistor can be obtained byreplacing the P-type and the N-type with each other in the layouts ofFIGS. 31A and 32.

The seventh embodiment utilizes this MIS transistor of the partialdepletion type of SOI structure.

FIG. 33A shows, by way of example, a structure of the semiconductordevice according to the seventh embodiment of the present invention. InFIG. 33A, a CMOS circuit is formed utilizing SOI transistors, or an MIStransistor of SOI structure. This CMOS circuit includes four CMOSinverters IV1-IV4. CMOS inverters IV1-IV4 include P-channel MIStransistors SPQ1-SPQ4 and N-channel MIS transistors SNQ1-SNQ4 eachhaving an SOI structure. Each of MIS transistors SPQ1-SPQ4 and SNQ1-SNQ4has a gate insulating film of thickness Tox, which in turn provides agate tunnel barrier similar to that provided by a silicon oxide film of3 nm in thickness.

In this structure, a large tunnel current may flow through the MIStransistor in the on state. For preventing this tunnel current flow,N-type body (N-body) regions of MIS transistors SPQ1-SPQ4 are coupledtogether, and the voltage on a common N-body region 76 is switched inaccordance with the standby cycle and the active cycle. In MIStransistors SNQ1-SNQ4, the voltage level of a P-body (P-type body)region 75 is likewise switched in accordance with the standby cycle andthe active cycle. More specifically, N-body region 76 is supplied with abias voltage, which turns off MIS transistors SPQ1-SPQ4, in the standbycycle. In the active cycle, a shallow bias is applied to N-body region76 of MIS transistors SPQ1-SPQ4 for operating MIS transistors SPQ1-SPQ4fast.

In MIS transistors SNQ1-SNQ4, the bias voltage on P-body region 75 isdeepened to turn off MIS transistors SNQ1-SNQ4 in the standby cycle sothat the off-leak current and gate tunnel current are reduced. In theactive cycle, the bias voltage on P-body region 75 is lowered to operateMIS transistors SNQ1-SNQ4 fast.

In the structure shown in FIG. 33A, the logical level of input signal INmay be unfixed in the standby cycle. Due to the bias voltages on N- andP-body regions 76 and 75, all MIS transistors SPQ1-SPQ4 and SNQ1-SNQ4are turned off regardless of the logical level of input signal IN, sothat both the gate tunnel current and the off-leak current can bereduced.

FIG. 33B is a signal waveform diagram representing an operation of thesemiconductor device shown in FIG. 33A. First, as shown in FIG. 33B,N-body region 76 is supplied with a high voltage Vpp in the standbycycle, and the threshold voltages of MIS transistors SPQ1-SPQ4 areincreased in absolute value, and these transistors SPQ1-SPQ4 are turnedoff regardless of the levels of voltage applied to their gates. InN-body region 76, high voltage Vpp prevents formation of an inversionlayer at an interface with the insulating film and therefore prevents agate tunnel current even when MIS transistors SPQ1-SPQ4 receive signalsat L-level on their gates. At most, a tunnel current occurs between thegate and drain. This tunnel current is extremely small and can beignored. In N-channel MIS transistors SNQ1-SNQ4, negative voltage VBB isapplied to P-body region 75 in the standby cycle, and MIS transistorsSNQ1-SNQ4 are turned off so that the gate tunnel current is sufficientlysuppressed.

In the active cycle, N-body region 76 is supplied with power supplyvoltage Vcc, and P-body region 75 is supplied with ground voltage GND(=Vss). In MIS transistors SPQ1-SPQ4 and SNQ1-SNQ4, the back gates andthe sources are at the same potential, and each threshold voltage isreduced to be sufficiently small in absolute value. Further, thesubstrate leak current does not occur and the junction capacitance issmall owing to the characteristics of the transistors of the SOIstructures. Accordingly, these transistors operate fast in the activecycle.

[Modification]

FIG. 34A shows a structure of a modification of the seventh embodimentof the present invention. In the structure shown in FIG. 34A, inputsignal IN is fixed to L-level in the standby cycle. MIS transistors SPQ1and SPQ3, which are turned on in the standby cycle, have the bodyregions commonly connected to N-body region 76 in accordance with thelogical level of input signal IN in the standby state. MIS transistorsSPQ2 and SPQ4, which are turned off in the standby cycle, have the bodyregions connected to the power supply node to be held at the samevoltage level as their respective sources. N-channel MIS transistorsSNQ1-SNQ4 are connected in a similar fashion. More specifically, MIStransistors SNQ2 and SNQ4, which are turned on in the standby cycle,have the body regions commonly coupled to P-body region 75. MIStransistors SNQ1 and SNQ3, which are turned off in the standby cycle,have the body regions coupled to the ground node so that the sources andthe body regions thereof are held at the equal voltage level.

All MIS transistors SPQ1-SPQ4 and SNQ1-SNQ4 have the SOI structures andeach have a gate insulating film of the small thickness (Tox). In thestandby cycle, as shown in FIG. 34B, high voltage Vpp is applied toN-body region 76, and negative voltage VBB is applied to P-body region75. Although input signal IN is at L-level, high voltage Vpp applied toN-body region 76 turns off MIS transistors SPQ1 and SPQ3, so that thegate tunnel currents are suppressed. In MIS transistors SNQ2 and SNQ4,P-body region 75 is at the negative voltage level, and MIS transistorsSNQ2 and SNQ4 are off, so that the gate tunnel currents are suppressed.

Accordingly, if the logical level of input signal IN in the standbycycle is known in advance, the bias of the body regions of the MIStransistors, which are on in the standby cycle, has only to be deepened,whereby the gate tunnel current can be suppressed even in the case wherethe gate insulating films are thin.

In the active cycle, N-body region 76 receives power supply voltage Vcc,and P-body region 75 receives ground voltage GND (=Vss). Therefore, MIStransistors SPQ1-SPQ4 and SNQ1-SNQ4 quickly produce output signal OUT inaccordance with input signal IN.

In the seventh embodiment, the previously described structure of thewell bias structure shown in FIG. 7 can be utilized as the structure forswitching the voltages on N- and P-body regions 76 and 75. In thesemiconductor device utilizing the MIS transistors of the SOI structure,the hierarchical power supply arrangement can also be utilized forreducing the off-leak current. Since the transistors, of which wellbiases are deep, have the sources connected to the main power supplyline or main ground line, the voltage level of an internal node can beheld in the fixed state in the standby state because the leak currentflows through the transistor deep in well bias. Therefore, such a statecan be prevented that the logical level of output signal OUT becomesunstable at the time of transition to the active cycle, and the fast andaccurate operation can be ensured.

According to the seventh embodiment of the present invention, asdescribed above, the bias of the body region of the transistor with theSOI structure is changed in accordance with the operation cycle, andtherefore the gate tunnel current can be suppressed even if thetransistor employs the SOI structure having a thin gate insulating film,and the semiconductor device which operates fast with low currentconsumption can be implemented.

Eighth Embodiment

FIG. 35 schematically shows a cross sectional structure of a buriedchannel MIS transistor used in an eighth embodiment of the presentinvention. In FIG. 35, buried channel MIS transistor includes impurityregions 81 and 82 formed spaced apart from each other at the surface ofsubstrate region 80, a thin gate insulating film 83 formed on a channelregion between impurity regions 81 and 82, and a gate electrode 84formed on a thin gate insulating film 83.

When the buried channel MIS transistor is on, a channel (inversionlayer) 85 thereof is formed in a substrate region that is slightlyspaced from the substrate surface. On the channel region surface, adepletion layer 86 expands from the source to the drain region. Underchannel (inversion layer) 85, a depletion layer 87 is formed.Capacitances of these depletion layers formed at the surface areequivalently added to the capacitance formed by gate insulating film 83.Therefore, the thickness of the gate insulating film for the gate tunnelcurrent equivalently increases so that the tunnel current betweeninversion layer 85 and gate electrode 84 can be suppressed. Therefore,this buried channel MIS transistor can be used as the MIS transistorhaving a large gate tunnel barrier. In other words, the buried MIStransistor can be utilized instead of the MIS transistor having a thickgate insulating film.

FIGS. 36A and 36B schematically show impurity profiles in the channelregion of the N-channel MIS transistor. More specifically, FIG. 36Ashows the channel impurity concentration profile of the structure with aP+ type polycrystalline silicon gate used as the gate electrode. In thestructure using the P+ type polycrystalline silicon as the gateelectrode, a difference in work function between the gate and the P-typesubstrate is small, and the depletion layer is hardly formed. Foradjusting the threshold voltage, the substrate surface is doped withN-type impurities, and then a deeper substrate portion is heavily dopedwith P-type impurities for forming an inversion layer.

In this structure, therefore, the channel region of the P-type substrateregion is of the N-type. In the on state, a depletion layer is formed inthis N-type impurity region, and an inversion layer is formed in theP-type impurity region. This inversion layer region is the channel, andthis N-channel MIS transistor can be used as the N-channel MIStransistor of the buried type.

FIG. 36B shows an impurity concentration profile in a case where an N+polycrystalline silicon gate is used in the N-channel MIS transistor. Inthe structure using the N+ polycrystalline silicon gate, a largedifference in work function is present between the gate and the P-typesemiconductor substrate region, and the depletion layer is formedeasily. In this case, therefore, a heavily doped P-type impurity regionis formed in the channel region so that the inverter layer is formed.The concentration of the P-type impurities at the substrate surface iscontrolled to adjust the threshold voltage. The channel region is formedat the surface of the P-type semiconductor substrate region so that theN-channel MIS transistor of the surface channel type is formed.

FIG. 37A shows an impurity concentration profile of the channel regionof the P-channel MIS transistor using an N-type semiconductor substrateregion. An N+ polycrystalline silicon gate is used as the gateelectrode. In the structure with the N+ polycrystalline silicon used asthe gate electrode, a difference in work function between the gate andthe N-type semiconductor substrate region is small, and the depletionlayer cannot be formed easily. Therefore, P-type impurities areimplanted into the channel region surface for the purpose of allowingeasy formation of the depletion layer and adjusting the thresholdvoltage, and a peak concentration region of N-type impurities is formedin a region deeper than the region doped with P-type impurities.

When the MIS transistor with N+ polycrystalline silicon gate is on,therefore, the P-type impurity region functions as the depletion layer,and the N-type impurity doped region functions as the inversion layer.In the structure shown in FIG. 37A, therefore, the P-channel MIStransistor of the buried channel type is formed.

In FIG. 37B, a P+ polycrystalline silicon gate is formed at the surfaceof the N-type semiconductor substrate region, and in this structure, alarge difference is present in work function between the gate electrodeand the substrate region, and therefore the depletion layer is formedeasily. The channel region surface is doped with N-type impurities foradjusting the threshold voltage, and an N-type impurity region having apeak concentration for forming the inversion layer is formed within thechannel region. In the structure shown in FIG. 37B, when the transistoris on, the inversion layer is formed entirely over the N-type impurityregion at the substrate surface. In the case of using P+ polycrystallinesilicon gate, a P-channel MIS transistor of the surface channel type isformed.

The peak concentration region in this MIS transistor of the surfacechannel type is formed at the depth substantially equal to the junctiondepth of the source/drain diffusion layers, and suppresses the increaseof the short-channel effect and the substrate bias effect.

Accordingly, by using the MIS transistors having the impurityconcentration profiles as shown in FIGS. 36A and 37A, the MIStransistors of the buried channel type can be implemented, and the gatetunnel currents can be suppressed.

FIG. 38A shows, by way of example, a semiconductor device according toan eighth embodiment of the present invention. Although the structureshown in FIG. 38A corresponds to the structure shown in FIG. 3, MIStransistors BQ1-BQ4 of the buried channel type are employed, instead ofthe MIS transistors having the gate insulating films of Tox2 inthickness as employed in the structure shown in FIG. 3.

As shown in FIG. 38B, input signal IN is at L-level in the standbycycle, and the MIS transistors which are turned on in the standby cycleare formed of MIS transistors BQ1-BQ4 of the buried channel type havinggate insulating film thickness Tox1, respectively. Even if the gateinsulating film has small thickness Tox1, the gate tunnel barrier can bemade large enough to prevent the gate tunnel current from flowing,because MIS transistors BQ1-BQ4 are of the buried channel type, and thedepletion layer is formed at the substrate surface in the on state toequivalently provide a large gate capacitance together with the gateinsulating film.

[Modification]

FIG. 39A shows a structure of a modification of the eighth embodiment ofthe present invention. The structure shown in FIG. 39A corresponds tothe semiconductor device shown in FIG. 19. Input signal IN shown in FIG.39A is at L-level in the standby cycle, as shown in FIG. 39B. In thisstructure, buried channel MIS transistors BQa, BQb, BQc and BQd are usedfor the MIS transistors which are on in the standby cycle. These MIStransistors BQa-BQd correspond to MIS transistors PQa, NQb, PQc and NQdshown in FIG. 19, respectively. Buried channel MIS transistors BQa-BQdhave the gate insulating films of Tox1 in thickness.

Control clock signals φ and /φ are at H- and L-levels in the standbystate, respectively, as shown in FIG. 39B. Therefore, switchingtransistors SWa and SWb are off in the standby cycle, and MIStransistors PQb, PQd, NQa and NQc having the gate insulating films ofTox1 in thickness hardly cause the gate tunnel current flow, andsuppress the off-leak currents.

MIS transistors BQa-BQd of the buried channel type each having gateinsulating film thickness Tox1 are on in the standby cycle, but have thegate insulating films equivalently increased owing to the depletionlayers formed at the channel region surfaces so that the gate tunnelcurrents are suppressed. Accordingly, by employing MIS transistorsBQa-BQd of the buried channel type for the respective MIS transistorswhich are turned on in the standby cycle, the gate tunnel currents canbe suppressed even if the gate insulating films are thin.

Power supply switching transistors SWa and SWb each may be formed of anMIS transistor of the buried channel type having thin gate insulatingfilm.

The MIS transistors of the buried channel type can be applied to the MIStransistors, in which a gate tunnel current may occur, of the first toseventh embodiments.

According to the eighth embodiment of the present invention, asdescribed above, the MIS transistors of the buried channel type are usedfor the respective MIS transistors, in which a gate tunnel current mayoccur, so that the gate tunnel current can be reliably suppressed, andthe power consumption of the semiconductor device in the standby statecan be reduced.

Ninth Embodiment

FIG. 40 schematically shows a cross sectional structure of an N-channelMIS transistor used in a ninth embodiment of the present invention. InFIG. 40A, the N-channel MIS transistor includes N-type impurity regions91 a and 91 b, which are formed, spaced away from each other, at asurface of P-type semiconductor substrate 90, as well as a gateelectrode 92 formed on a channel region between impurity regions 91 aand 91 b with a gate insulating film 94 underlaid. Gate electrode 92 isdoped with N-type impurity at a concentration slightly smaller than thatof an N+ doped polycrystalline silicon gate in a normal surface channeltype MIS transistor. In the structure using N− doped polycrystallinesilicon for gate electrode 92, an inversion layer 93 is formed in thechannel region of P-type substrate 90 when the MIS transistor is on.

In this state, a depletion layer 92 a is formed more widely in gateelectrode 92 that is in contact with gate insulating film 94. This isfor the following reason. In the case where N doped polycrystallinesilicon is used for gate electrode 92, the majority carriers are lessand the energy band bending occurs to a larger extent, and the depletionlayer is more likely to be formed, compared with the case using N+ dopedpolycrystalline silicon for the gate electrode. Depletion layer 92 a isa region where electric charges are not present, and serves as aninsulating film. Therefore, gate insulating film 94 and wide depletionlayer 92 a are interposed between gate electrode 92 and inversion layer93 so that the insulating film for the gate tunnel current equivalentlyincreases in thickness, and the gate tunnel barrier increases in height.Accordingly, the gate tunnel current can be suppressed by depletionlayer 92 a even in the structure using a thin gate insulating filmhaving thickness Tox1.

FIG. 40B schematically shows a cross sectional structure of a P-channelMIS transistor used in the ninth embodiment of the present invention. InFIG. 40B, P-channel MIS transistor includes P-type impurity regions 96 aand 96 b formed, spaced apart from each other, at a surface of an N-typesubstrate 95, and a gate electrode 97 formed on a channel region betweenimpurity regions 96 a and 96 b with a gate insulating film 99 underlaid.Gate electrode 97 is formed of P doped polycrystalline silicon. This MIStransistor is of a surface channel type. However, a concentration ofP-type impurities in gate electrode 97 is small. Therefore, in the casewhere an inversion layer 98 is formed in a channel region when this MIStransistor is on, a wider depletion layer 97 a is formed in gateelectrode 97 as a result of less majority carrier and band bending atthe insulating film interface.

In the structure shown in FIG. 40B, therefore, a gate insulating film 99and the wide depletion layer 97 a are disposed between gate electrode 97and inversion layer 98 so that the thickness of gate insulating film 99can be equivalently increased, and the gate tunnel current can besuppressed.

In this ninth embodiment, the MIS transistors of the gate depletion typeshown in FIGS. 40A and 40B are used as MIS transistors having large gatetunnel barriers.

FIG. 41 shows, by way of example, the structure of the semiconductordevice according to the ninth embodiment of the present invention. Thestructure of the semiconductor device shown in FIG. 41 corresponds tothe structure of the semiconductor device shown in FIG. 3. The structureshown in FIG. 41 uses MIS transistors GQ1-GQ4 of the gate depletion typeeach having a gate insulating film of thickness Tox1, instead of MIStransistors PQ1, PQ3, NQ2 and NQ4 having thick gate insulating films asshown in FIG. 3. Input signal IN is at L-level in the standby state.Therefore, MIS transistors GQ1-GQ4 of the gate depletion type are usedfor the MIS transistors that are on and may cause gate tunnel currentsin the standby state. The MIS transistors of the surface channel typeeach having a gate insulating film of thickness Tox1 are used for theother MIS transistors NQ1, PQ2, NQ3 and PQ4 that are on in the standbystate. Each of MIS transistors GQ1-GQ4 of the gate depletion type has awide depletion layer formed extending from the interface between thegate electrode and the insulating film into the gate electrode whenturned on, and thereby the gate tunnel current is suppressed. Therefore,the gate tunnel current can be sufficiently suppressed even when thegate insulating film has sufficiently small thickness Tox1.

[Modification]

FIG. 42 shows a structure of a semiconductor device of a modification ofan ninth embodiment of the present invention. The semiconductor deviceshown in FIG. 42 corresponds to the semiconductor device having thehierarchical power supply structure shown in FIG. 19. In thesemiconductor device shown in FIG. 42, MIS transistors GQa, GQb, GQc andGQd are used instead of MIS transistors PQa, PQc, NQb and NQd which areon in the standby cycle. Structures other than the above are thesubstantially same as those shown in FIG. 19.

In the hierarchical power supply structure shown in FIG. 42, MIStransistors GQa-GQd of the gate depletion type are used for the MIStransistors that are on in the standby state and may cause gate tunnelcurrents therein. Therefore, in the structure shown in FIG. 42, the gatetunnel current in the standby state can be suppressed, and the off-leakcurrent flowing through the MIS transistor in the off state can also bereduced.

MIS transistors of the gate depletion type each having the gateinsulating film of thickness Tox1 may be used for switching transistorsSWa and SWb. MIS transistors of another type having large gate tunnelbarriers may be used for the switching transistors.

The MIS transistor of the gate depletion type described above may beapplied to the MIS transistors, which may cause the gate tunnel currentstherein, in the first to seventh embodiments.

According to the ninth embodiment of the present invention, as describedabove, the MIS transistor of the gate depletion type is used for the MIStransistor that is on in the standby state. Therefore, the gate tunnelcurrent in the standby state can be reduced, and thereby the currentconsumption in the standby state can be reduced.

Tenth Embodiment

FIG. 43 shows a structure of a semiconductor device according to a tenthembodiment of the present invention. In FIG. 43, the semiconductordevice includes four CMOS inverter circuits IVa-IVd. The output of CMOSinverter circuit IVc is fed back to an input of CMOS inverter circuitIVb. Therefore, CMOS inverter circuits IVb and IVc form an inverterlatch.

CMOS inverter circuit IVa includes P- and N-channel MIS transistors PT1and NT1, and CMOS inverter circuit IVd includes P- and N-channel MIStransistors PT2 and NT2. Each of MIS transistors PT1, PT2, NT1 and NT2has a gate insulating film of thickness Tox1.

CMOS inverter circuit IVb includes P- and N-channel MIS transistors PTR1and NTR1. CMOS inverter circuit IVc includes P- and N-channel MIStransistors PTR2 and NTR2. Each of CMOS inverter circuits IVa-IVd usesthe voltage on power supply node 1 and the voltage on ground node 2 asits operation power supply voltages.

MIS transistors PTR1, PTR2, NTR1 and NTR2 included in CMOS invertercircuits IVb and IVc have larger gate tunnel barriers than thetransistors in CMOS inverter circuits IVa and IVd. These MIS transistorsPTR1, PTR2, NTR1 and NTR2 may be MIS transistors having thick gateinsulating films, or may be MIS transistors having deep well biases.Further, these MIS transistors PTR1, PTR2, NTR1 and NTR2 may be of theburied channel type or of the gate depletion type. In the followingdescription, the MIS transistor which has a large gate tunnel barriersuppressing the gate tunnel current will be referred to as a“tunnel-current-reduced MIS transistor” or an “ITR transistor”hereinafter. MIS transistors having thin gate insulating films are usedin circuits such as a logic circuit other than the above semiconductordevice.

As shown in FIG. 43, ITR transistors PTR1, PTR2, NTR1 and NTR2 areutilized in the latch circuit, and the ITR transistors are used betweenpower supply node 1 and ground node 2 so that the gate tunnel currentcan be suppressed even in such a case that the logic level of the inputsignal IN changes in accordance with the operating state, and thereforethe logical levels in the standby state of the latch signals ofinverters IVb and IVc forming the latch circuit cannot be predicted.

[First Modification]

FIG. 44 shows a structure of a first modification of the tenthembodiment of the present invention. In FIG. 44, the semiconductordevice includes a clocked CMOS inverter circuit for latching signals onnodes 100 a and 100 b. Clocked CMOS inverter circuit includes ITRtransistors PTR3, NTR3 and NTR4 connected in series between power supplynode 1 and ground node 2. The gates of ITR transistors PTR3 and NTR3 areconnected to node 100 b. ITR transistor NTR4 is supplied, on its gate,with a set signal SET.

The other CMOS inverter circuit includes ITR transistors PTR4, NTR5 andNTR6 connected in series between power supply node 1 and ground node 2.The gates of ITR transistors PTR4 and NTR5 are connected to node 100 a,and ITR transistor NTR6 is supplied with a reset signal RST on its gate.Output signal OUT is generated from node 100 b.

The semiconductor device further includes transistors for establishingthe signal states of nodes 100 a and 100 b, and more specificallyincludes a P-channel ITR transistor PTR5 which is turned on in responseto set signal SET to transmit the voltage on power supply node 1 to node100 a, and a P-channel ITR transistor PTR6 which is turned on totransmit the voltage on power supply node 1 to node 100 b when resetsignal RST is at L-level. ITR transistors PTR3-PTR6 and NTR3-NTR6 havesufficiently large gate tunnel barriers, and can suppress the gatetunnel currents, as already described. An operation of the semiconductordevice shown in FIG. 44 will now be described with reference to a signalwaveform diagram of FIG. 45.

In the standby state (latch state), set signal SET and reset signal RSTare both at H-level, and both ITR transistors PRT5 and PTR6 are offwhile ITR transistors NTR4 and NTR6 are on. Therefore, nodes 100 a and100 b are held in the set or reset state. MIS transistors NTR4 and NTR6are ITR transistors, and gate tunnel currents thereof are sufficientlysmall even in the on state. MIS transistors PTR3, PTR4, NTR3 and NTR5are likewise ITR transistors, and gate tunnel currents thereof aresufficiently small. Therefore, the gate tunnel currents are sufficientlysuppressed regardless of the signal voltage levels of nodes 100 a and100 b, or regardless of the signal level of latch signal of the CMOSinverter latch.

When set signal SET falls to L-level, ITR transistor PTR5 is turned on,and ITR transistor NTR4 is turned off so that node 100 a is driven tothe power supply voltage level. ITR transistor PTR6 is off. When thevoltage on node 100 a attains H-level, the CMOS inverter circuit formedof ITR transistors PTR4, NTR5 and NTR6 sets the voltage level of node100 b to L-level. When set signal SET attains H-level, nodes 100 a and100 b are held at H- and L-level, respectively. Therefore, output signalOUT falls from H-level to L-level in response to falling of set signalSET (i.e., the state changes from the reset state to the set state).

When reset signal RST falls to L-level under the set state, ITRtransistor PTR6 is turned on, and ITR transistor NTR is turned off. Node100 b is driven to H-level so that ITR transistors PTR3, NTR3 and NTR4drive node 100 a to L-level. When reset signal RST rises to H-level,nodes 100 a and 100 b are held at L- and H-levels, respectively.Therefore, output signal OUT rises to H-level when reset signal RSTfalls to L-level.

When the semiconductor device shown in FIG. 44 is to be operated, setsignal SET and reset signal RST are driven to L-level, or to the set andreset states in the operation. However, in the standby state where bothset signal SET and reset signal RST are held at H-level, nodes 100 a and100 b are held at H- and L-levels, or at L- and H-levels, respectively.Even in this state, the gate tunnel current is sufficiently suppressedbecause the ITR transistor is used in the CMOS inverter latch circuit.

ITR transistor PTR5 for setting and ITR transistor PTR6 for resettingare off in the standby state, and are selectively turned on only uponsetting or resetting. Accordingly, ITR transistors PTR5 and PTR6 may beformed of MIS transistors having thin gate insulating films.

[Second Modification]

FIG. 46 shows a structure of a second modification of the tenthembodiment of the present invention. In FIG. 46, P- and N-channel MIStransistors PTR7 and NTR7 connected between power supply node 1 andground node 2 form one CMOS inverter circuit. Likewise, P- and N-channelMIS transistors PTR8 and NTR8 connected between power supply node 1 andground node 2 form another CMOS inverter circuit. These CMOS invertercircuits form a latch circuit. The drains of MIS transistors PTR8 andNTR8 are connected to the gates of MIS transistors PTR7 and NTR7. Thedrains of MIS transistors PTR7 and NTR7 are connected to the gates ofMIS transistors PTR8 and NTR8. MIS transistors PTR7, PTR8, NTR7 and NTR8are formed of ITR transistors, respectively. The gates of MIStransistors PTR7 and NTR7 are connected to a transfer gate XF1, which isturned on in response to control clock signals φX and /φX. Flow ofsignals via transfer gate XF1 depends on the current drive capabilitiesof MIS transistors PTR7, PTR8, NTR7 and NTR8. If the CMOS invertercircuit formed of MIS transistors PTR8 and NTR8 have large current drivecapabilities, signals are output from the latch circuit via transfergate XF1. In the case where MIS transistors PTR7 and NTR7 have largercurrent capabilities, An external signal is applied to this latchcircuit via transfer gate XF1.

In the standby state, control clock signals φX and /φX are at L- andH-levels, respectively, transfer gate (transmission gate) XF1 is off,and MIS transistors PTR7, PTR8, NTR7 and NTR8 are in the latch state. Inthis state, the logical level of the latch signal depends on the logicallevel of the signal which was applied in the last active cycle. However,MIS transistors PTR7, PTR8, NTR7 and NTR8 are all formed of the ITRtransistors, respectively, and the gate tunnel currents are sufficientlysuppressed regardless of the logical level of the latch signal.

In the standby state, transfer gate XF1 is off, and the gate tunnelcurrent hardly occurs. Therefore, a problem of increase in gate tunnelcurrent does not occur even if transfer gate XF1 is formed of MIStransistors having thin gate insulating films.

According to the tenth embodiment of the present invention, as describedabove, the latch circuit is formed of the ITR transistors, and the gatetunnel current during the latching state can be suppressed.

Eleventh Embodiment

FIG. 47 shows a structure of a semiconductor device according to aneleventh embodiment of the present invention. In FIG. 47, thesemiconductor device includes an active latch circuit AL which is madeactive and latches a received signal in the active period, and a standbylatch circuit SL which holds the latch signal of active latch circuit ALduring the standby period. Active latch circuit AL is coupled to a logiccircuit via a transfer gate XF2, which is turned on in response tocontrol clock signals φX and /φX.

Active latch circuit AL includes a CMOS inverter circuit formed of MIStransistors PQ10 and NQ10, and a CMOS inverter circuit formed of MIStransistors PQ11 and NQ11. These CMOS inverter circuits are coupled to apower supply node 101 and a ground node 102. A drain node 106 a of MIStransistors PQ11 and NQ11 is coupled to gates of MIS transistors PQ10and NQ10. Transfer gate XF2 is coupled to the gates of MIS transistorsPQ10 and NQ10. MIS transistors PQ10, PQ11, NQ10 and NQ11 each have agate insulating film of the small thickness Tox1.

Standby latch circuit SL includes a CMOS inverter circuit formed of P-and N-channel MIS transistors PTR10 and NTR10 coupled between powersupply node 1 and ground node 2, as well as P- and N-channel MIStransistors PTR11 and NTR11 coupled in series between power supply node1 and ground node 2. These MIS transistors PTR10, PTR11, NTR10 and NTR11are ITR transistors, in which gate tunnel currents are reduced. A drainnode 106 b of MIS transistors PTR11 and NTR11 is connected to the gatesof MIS transistors PTR10 and NTR10. Each of latch circuits AL and SL isformed of a so-called inverter latch circuit.

This semiconductor device further includes a bidirectional transfercircuit 105 for bidirectionally transferring signals between the drainnodes 106 a and 106 b in accordance with transfer control signals φA andφB. Bidirectional transfer circuit 105 includes a clocked invertercircuit 105 responsive to a transfer instructing signal φA for invertingthe signal on the drain node 106 a for transmission to the drain node106 b, and a clocked inverter circuit 105 b for transferring the signalon the node 106 b to the node 106 a in accordance with a transferinstructing signal φB.

In transition from the active period to the standby period, transferinstructing signal φA is activated, and the signal on the node 106 a istransmitted to node 106 b. In transition from the standby period to theactive period, transfer instructing signal φB is activated, and thesignal on the node 106 b which is latched by standby latch circuit SL istransferred to active latch circuit AL. An operation of semiconductordevice shown in FIG. 47 will now be described with reference to a signalwaveform diagram of FIG. 48.

In the active period, control clock signal φX is at H-level, andtransfer gate XF2 is on so that active latch circuit AL is coupled tothe logic circuit. Active latch circuit AL latches the signal appliedfrom the logic circuit, or applies the signal, which is latched byactive latch circuit AL, to the logic circuit.

When the standby period starts subsequently to the completion of theactive period, transfer instructing signal φA is activated, and thesignal on the node 106 a is transmitted to the node 106 b. Standby latchcircuit SL latches the signal on the node 106 b. After completion of thesignal transfer to standby latch circuit SL, supply of the power supplyvoltage to power supply node 101 stops, or a gate tunnel currentreducing circuit provided for the nodes 101 and 102 is activated, sothat the gate tunnel current in active latch circuit AL is reduced orsuppressed.

In active latch circuit AL, therefore, the signal held on the node 106 abecomes unstable after completion of the signal transfer to standbylatch circuit SL. In contrast, standby latch circuit SL is alwayssupplied with the operation power supply voltage from power supply node1, and reliably latches the signal on node 106 b.

In transition to the active period after completion of the standbyperiod, transfer instructing signal φB is first activated, and thesignal on node 106 b is transmitted to node 106 a via clocked invertercircuit 105 b. Thereby, active circuit AL returns to the state ofholding the signal latched in the last active cycle. Before activationof transfer instructing signal φB, power supply voltage Vcc and groundvoltage GND (=Vss) are supplied to power supply node 101 and ground node102 of active latch circuit AL, respectively.

When the signal transfer to active latch circuit AL is completed,control clock signal φX attains H-level, and active latch circuit AL iscoupled to the logic circuit.

During the standby period, therefore, standby latch circuit SL includingITR transistors as its components latches a signal, and the active latchcircuit is set to the state where the gate tunnel current is suppressed.Accordingly, the current consumption in the standby state can bereduced. In transition to the active period, the signal saved in standbylatch circuit SL is transferred to active latch circuit AL so that theactive latch circuit AL can be accurately restored to the originalstate.

FIG. 49A schematically shows a structure of a portion for generatingtransfer instructing signals φA and φB shown in FIG. 47. In FIG. 49A,the transfer instructing signal generating portion includes: a modedetecting circuit 110 which generates a standby instructing signal φSTBin accordance with an operation mode instructing signal CMD; a one shotpulse generating circuit 111 which produces a one shot pulse signal inresponse to activation of standby instructing signal φSTB received frommode detecting circuit 110; an inverter 112 which inverts standbyinstructing signal φSTB; a one shot pulse generating circuit 113 whichgenerates a one shot pulse signal in response to rising of the outputsignal of inverter 112; and an NOR circuit 115 which receives the outputsignal of one shot pulse generating circuit 113 and standby instructingsignal φSTB generated from mode detecting circuit 110.

One shot pulse generating circuit 111 generates transfer instructingsignal φA, and one shot pulse generating circuit 113 generates transferinstructing signal φB. NOR circuit 115 generates control clock signalφX. An operation of the transfer instructing signal generating portionshown in FIG. 49A will now be described with reference to a signalwaveform diagram of FIG. 49B.

During the active period, mode detecting circuit 110 keeps standbyinstructing signal φSTB at L-level. Therefore, one shot pulse signals φAand φB are not generated. Accordingly, control clock signal φX from NORcircuit 115 is at H-level in the active period, and transfer gate XF2shown in FIG. 47 is conductive.

If operation mode instructing signal CMD applied to mode detectingcircuit 110 is an active period stop instructing signal (e.g., a sleepmode instructing signal), mode detecting circuit 110 raises standbyinstructing signal φSTB to H-level. In response to the rising of standbyinstructing signal φSTB, one shot pulse generating circuit 111 generatesa one shot pulse signal so that transfer instructing signal φA isactivated. In this operation, control clock signal φX from NOR circuit115 falls to L-level in response to rising of standby instructing signalφSTB. Accordingly, when transfer gate XF2 shown in FIG. 47 isnon-conductive, bidirectional transfer circuit 105 transfers the signalfrom active latch circuit AL to standby latch circuit SL. When transferinstructing signal φA is deactivated, a mechanism for reducing the gatetunnel current (gate tunnel current reducing mechanism) of active latchcircuit AL is deactivated (activation of the gate tunnel currentreducing mechanism, or stop of supply of power supply voltage).

When operation mode instructing signal CMD is the standby period stopinstructing signal (e.g., sleep mode stop instructing signal), modedetecting circuit 110 lowers standby instructing signal φSTB to L-level.In response to falling of standby instructing signal φSTB, the outputsignal of inverter 112 rises, and one shot pulse generating circuit 113generates a one shot pulse signal so that transfer instructing signal φBis activated. Even when standby instructing signal φSTB attains L-level,transfer instructing signal φB is at H-level so that control clocksignal φX maintains the L-level. In accordance with standby instructingsignal φSTB, the gate tunnel current reducing mechanism is deactivatedso that active latch circuit AL is supplied with the operation powersupply voltage. Therefore, by transferring the signal from standby latchcircuit SL to active latch circuit AL in response to activation oftransfer instructing signal φB, active latch circuit AL reliably latchesthe transferred signal.

In the structure shown in FIG. 49A, NOR circuit 115 may be replaced witha set/reset flip-flop that is set in response to rising of transferinstructing signal φB and is reset in response to falling of standbyinstructing signal φSTB. With such flip-flop, after transfer instructingsignal φB is deactivated and the transfer of the signal from standbylatch circuit SL to active latch circuit AL is completed, control clocksignal φX can be reliably set to H-level.

The gate tunnel current reducing mechanism for active latch circuit ALmay be adapted to be deactivated in response to deactivation of standbyinstructing signal φSTB, and to be activated in response to falling oftransfer instructing signal φA. For example, a rise-delayed signal ofstandby instructing signal φSTB can be utilized as the signal forcontrolling the gate tunnel current reducing mechanism of active latchcircuit AL.

Control clock signal φX may be formed of an inverted, fall-delayedsignal of standby instructing signal φSTB.

[First Modification]

FIG. 50 is a signal waveform diagram representing an operation of afirst modification of the eleventh embodiment of the present invention.This first modification utilizes the semiconductor device shown in FIG.47, and thus utilizes active latch circuit AL and standby latch circuitSL. Bidirectional transfer circuit 105 transfers the signal betweenactive latch circuit AL and standby latch circuit SL.

In the structure of the first modification, transfer instructing signalφA changes in synchronization with control clock signal φX. During theactive period, therefore, the latch signal of active latch circuit AL istransmitted to standby latch circuit SL via bidirectional transfercircuit 105. During the active period, therefore, an operation on activelatch circuit AL is effected, and a change in signal level of activelatch circuit AL is transmitted to standby latch circuit SL viabidirectional transfer circuit 105 without a delay when a change occursin logical level of the latch signal of active latch circuit AL.

In the standby cycle, control clock signal φX attains L-level, andtransfer gate XF2 is off. Also, transfer instructing signal φA is atL-level, and clocked inverter circuit 105 a is in the outputhigh-impedance state. In response to deactivation of control clocksignal φX, active latch circuit AL and standby latch circuit SL areisolated from each other. In active latch circuit AL, the gate tunnelcurrent reducing mechanism is activated, and the latch signal of activelatch circuit AL is in the indefinite state. However, standby latchcircuit SL continues latching of the received signal during the standbyperiod because the power supply voltage is still supplied.

In transition to the active period after the standby period, transferinstructing signal φB is first activated, and the signal latched instandby latch circuit SL is transferred to active latch circuit AL viabidirectional transfer circuit 105. In this case, the gate tunnelcurrent reducing mechanism of active latch circuit AL is already madeinactive, and active latch circuit AL reliably latches the signalapplied from standby latch circuit SL via bidirectional transfer circuit105.

When transfer instructing signal φB is deactivated, control clock signalφX and transfer instructing signal φA attains H-level of the activestate. Therefore, a change in latch signal of active latch circuit AL isimmediately transmitted to standby latch circuit SL.

This standby latch circuit SL is formed of the ITR transistors havinglarge gate tunnel barriers, and therefore operate more slowly than anMIS transistor having a thin gate insulating film. Therefore, bytransferring the latch signal from active latch circuit AL to standbylatch circuit SL during the active period, it is not necessary toconsider the latch/transfer timing, and the transfer period upontransition to the active period can be shortened. Further, a signal canbe accurately transferred from active latch circuit AL to standby latchcircuit SL for latching it by standby latch circuit SL.

Although the operation speed of standby latch circuit SL is slower thanthat of active latch circuit AL, standby latch circuit SL merely latchesthe signal in the standby state, and the latched signal is in the fixedstate. In transition from the standby period to the active period,active latch circuit AL can accurately and quickly latch the transferredsignal in accordance with the latch signal of standby latch circuit SLwhen the signal is transferred to active latch circuit AL viabidirectional transfer circuit 105.

FIG. 51A schematically shows a structure of a control signal generatingportion, which generates a control clock signal φX as well as transferinstructing signals φA and φB shown in FIG. 50. In FIG. 51A, the controlsignal generating portion includes: a mode detecting circuit 115 whichactivates standby instructing signal φSTB when the standby mode isinstructed in accordance with operation mode instructing signal CMD; aset/reset flip-flop 117 which is set in response to the rising ofstandby instructing signal φSTB; an inverting and delaying circuit 116which generates a signal by inverting and delaying by a predeterminedperiod the standby instructing signal φSTB; and a one shot pulsegenerating circuit 118 which generates a one shot pulse signal inresponse to the rising of the output signal of inverting and delayingcircuit 116.

Set/reset flip-flop 117 is reset in response to falling of the one shotpulse generated from one shot pulse generating circuit 118. Set/resetflip-flop 117 generates transfer instructing signal φA and control clocksignal φX from its output Q. An operation of the control signalgenerating portion shown in FIG. 51A will now be described withreference to a signal waveform diagram of FIG. 51B.

In the active period, standby instructing signal φSTB is at L-level, andset/reset flip-flop 17 is in the reset state. Control clock signal φXand transfer instructing signal φA are both at H-level. When operationmode instructing signal CMD designates the standby mode, standbyinstructing signal φSTB rises to H-level. In response to the rising ofstandby instructing signal φSTB, set/reset flip-flop 117 is set to lowercontrol clock signal φX and transfer instructing signal φA from H-levelto L-level. At this time, control of the power supply voltage of activelatch circuit AL (activation of the gate tunnel current reducingmechanism by stop of supply of the power supply voltage and others) isperformed in response to the falling of standby instructing signal φSTB.

When the operation mode instructing signal CMD instructs the stop of thestandby period, standby instructing signal φSTB generated from modedetecting circuit 115 is deactivated. Inverting and delaying circuit 116delays standby instructing signal φSTB by a predetermined time. For thedelay time of inverting and delaying circuit 116, recovery of the powersupply for active latch circuit AL (deactivation of the gate tunnelcurrent reducing mechanism) is performed in response to deactivation ofstandby instructing signal φSTB. When a predetermined period of timeelapses, the output signal of inverting and delaying circuit 116 rises,and the transfer instructing signal φB generated from one shot pulsegenerating circuit 118 is activated for a predetermined period. Aftertransfer instructing signal φB reaches L-level, set/reset flip-flop 117is reset, and transfer instructing signal φA and control clock signal φXrise to H-level. Responsively, active latch circuit AL is coupled to thelogic gate via transfer gate XF2 after the signal is transferred fromstandby latch circuit SL to active latch circuit AL.

After recovery of the power supply voltage for active latch circuit AL,the latch signal is transferred from standby latch circuit SL to activelatch circuit AL, and therefore active latch circuit AL can accuratelylatch the transferred signal.

In clocked inverter circuits 105 a and 105 b of the bidirectionaltransfer circuit, both the gate tunnel current and the sub-thresholdleak current (off-leak current) can be reduced by employing ITRtransistors as the MIS transistors in the clock controlled portion.

[Second Modification]

FIG. 52 is a signal waveform diagram representing an operation of asecond modification of the eleventh embodiment of the present invention.A semiconductor device employed for the operation in FIG. 52 includesactive latch circuit AL and standby latch circuit SL as well asbidirectional transfer circuit 105 shown in FIG. 47. In this secondmodification, data transfer is executed between active latch circuit ALand standby latch circuit SL in accordance with an active cycleinstructing signal φACTA, which instructs the cycle for an operation toactive latch circuit AL.

When active cycle instructing signal φACTA is activated, transferinstructing signal φB is first activated, and bidirectional transfercircuit 105 executes data transfer from standby latch circuit SL toactive latch circuit AL. At this point of time, power supply voltage isalready stabilized in active latch circuit AL. Then, transferinstructing signal φB is deactivated, and signal transfer from standbylatch circuit SL to active latch circuit AL is completed. Then, controlclock signal φX becomes active, and transfer gate XF2 is turned on.Responsively, active latch circuit AL is coupled to the correspondinglogic circuit, and processing such as transfer of the latch signal orlatching of the signal received from the logic circuit is executed.

When the processing for active latch circuit AL is completed, transferinstructing signal φA is activated with a predetermined delay fromrising of control clock signal φX. In accordance with this activation oftransfer instructing signal φA, clocked inverter circuit 105 a isactivated, and the signal is transferred from active latch circuit AL tostandby latch circuit SL. When a predetermined time elapses aftercompletion of the signal transfer from active latch circuit AL tostandby latch circuit SL, active cycle instructing signal φACTA isdeactivated, and the operation cycle for active latch circuit AL iscompleted.

In response to this deactivation of active cycle instructing signalφACTA, the power supply voltage for active latch circuit AL is socontrolled as to reduce the gate tunnel current (e.g., by stoppingsupply of the power supply voltage). Standby latch circuit SL receivesand latches the signal held by active latch circuit AL in response toactivation of transfer instructing signal φA in a period of the activestate of active cycle instructing signal φACTA. Therefore, fastoperation performance can be ensured without adversely affecting thelogical processing speed in the active period, and further the currentconsumption during the active period can be reduced. Thereafter, theabove operation is repeated every time the operation for the activelatch circuit AL is performed.

FIG. 53 schematically shows a structure of a control signal generatingportion generating the respective signals shown in FIG. 52. In FIG. 53,the control signal generating portion includes: a mode detecting circuit120 for generating active cycle instructing signal φACTA indicative of aperiod, for which the operation for active latch circuit AL is to beperformed, in accordance with operation mode instructing signal CMD; aone shot pulse generating circuit 121 which generates a one shot pulsesignal in response to activation of active cycle instructing signalφACTA generated from mode detecting circuit 120; an inverter circuit 122which inverts the pulse signal received from one shot pulse generatingcircuit 121; an AND circuit 123 which receives the output signal ofinverter circuit 122 and active cycle instructing signal φACTA; a oneshot pulse generating circuit 124 which generates a one shot pulsesignal in response to rising (activation) of the output signal of ANDcircuit 123; a delay circuit 125 which delays by a predetermined timethe pulse signal generated by one shot pulse generating circuit 124; anda one shot pulse generating circuit 126 which generates a one shot pulsesignal in response to rising of the output signal of delay circuit 125.

One shot pulse generating circuits 121 and 126 generate transferinstructing signals φB and φA, respectively. One shot pulse generatingcircuit 124 generates control clock signal φX. Delay circuit 125 has adelay time equal to a period required for such an operation thatprocessing is effected on the signal for active latch circuit AL and thelatch signal of active latch circuit AL attains the definite state.

In the control signal generating portion shown in FIG. 53, whenoperation mode instructing signal (or command) CMD is applied, modedetecting circuit 120 activates active cycle instructing signal φACTAfor a period of the operation on active latch circuit AL being active.This corresponds, for example, to such a structure that the whole deviceincluding the active latch circuit operates in synchronization with aclock signal CLK, and active cycle instructing signal φACTA is activatedfor a predetermined period of time at the same timing as activation ofthe active latch circuit after elapsing of predetermined number ofcycles of this clock signal CLK when operation mode instructing signalCMD instructs a certain operation mode.

When active cycle instructing signal φACTA is activated, transferinstructing signal φB generated from one shot pulse generating circuit121 is activated, and the signal transfer from standby latch circuit SLto active latch circuit AL is performed. When active cycle instructingsignal φACTA is made active, and transfer instructing signal φB is madeinactive, one shot pulse generating circuit 124 activates control clocksignal φX. Thus, control clock signal φX is activated, and active latchcircuit AL is coupled to the corresponding logic circuit after the powersupply voltage is recovered in active latch circuit AL owing to thepower supply control by active cycle instructing signal φACTA, and afterthe data transfer from standby latch circuit SL is completed.

When control clock signal φX is activated, transfer instructing signalφA is generated by one shot pulse generating circuit 126 after elapsingof the delay time of delay circuit 125. Therefore, transfer instructingsignal φA is activated to execute the signal transfer from active latchcircuit AL to standby latch circuit SL after the signal processing foractive latch circuit AL by the logic circuit is completed, and the latchsignal of active latch circuit AL is fixed. Within the cycle ofexecution of the processing on active latch circuit AL, the signal ofstandby latch circuit SL is transferred. Therefore, an additional cycleis not required for this transfer. Further, the signal transfer fromactive latch circuit AL to standby latch circuit SL does not adverselyaffect the processing operation of the logic circuit, and reduction inoperation speed of the whole device can be prevented.

When transfer instructing signal φA is activated, control clock signalφX is deactivated in accordance with appropriate timing, and transfergate XF2 is turned off.

[Third Modification]

FIG. 54 is a signal waveform diagram representing an operation of athird modification of the eleventh embodiment of the present invention.In the third modification, clock signal CLK defines the operation cycle.The structure of the semiconductor device is the same as that shown inFIG. 47, and includes active latch circuit AL, standby latch circuit SL,bidirectional transfer circuit 105 for signal transfer between latchcircuits AL and SL, and transfer gate XF2 which couples active latchcircuit AL to the logic circuit. An operation of the third modificationwill now be described with reference to a signal waveform diagram ofFIG. 54.

In a cycle #1 of clock signal CLK, active cycle instructing signal φACTAis activated in accordance with an operation mode instructing signal. Inaccordance with activation of active cycle instructing signal φACTA,power supply recovery processing for active latch circuit AL isperformed. When this processing of recovery of the power supply foractive latch circuit AL is completed, transfer instructing signal φB isactivated, and the signal latched on node 106 b of standby latch circuitSL is transferred to node 106 a of active latch circuit AL viabidirectional transfer circuit 105. Responsively, the signal potentialon node 106 a of active latch circuit AL attains the level determined bythe latch signal of standby latch circuit SL.

In a cycle #2 of clock signal CLK, control clock signal φX which is anactivating signal for active latch circuit AL is made active, and activelatch circuit AL is coupled to the logic circuit via transfer gate XF2.The logic circuit predeterminedly processes the signal latched by activelatch circuit AL.

In this cycle #2 of clock signal CLK, necessary processing is performed,and the signal for active latch circuit AL is processed. In accordancewith this signal processing, the signal potential on node 106 a ofactive latch circuit AL changes. The timing of this change is determinedby the signal processing timing of the logic circuit. Accordingly, FIG.54 shows the timing of signal potential change of node 106 a as it has acertain time width.

After the processing for active latch circuit AL is completed in clockcycle #2, control clock signal φX is deactivated in a next cycle #3.Subsequently to the deactivation of control clock signal φX, transferinstructing signal φA is activated, and the signal latched by activelatch circuit AL is transferred to standby latch circuit SL. When thesignal transfer to standby latch circuit SL is completed, the powersupply for active latch circuit AL is so controlled as to reduce thegate tunnel current.

Active cycle instructing signal φACTA may be inactive in clock cycle #3,or may be held in the active state while other logic circuits areoperating.

As shown in FIG. 54, a signal is transferred from active latch circuitAL to standby latch circuit SL in the cycle following the cycle in whichthe signal processing for active latch circuit AL is performed. Thereby,it is not necessary to consider the time for transfer from active latchcircuit AL to SL when determining the cycle period of the clock signal,and the fast operation feature is not adversely affected. Further, it ispossible to reduce the current consumption of active latch circuit AL inthe standby state (standby cycle).

FIG. 55 schematically shows a structure of a control signal generatingportion for generating various signals shown in FIG. 54. In FIG. 55, thecontrol signal generating portion includes: a mode detecting circuit 130which receives operation mode instructing signal CMD and clock signalCLK, and activates active cycle instructing signal φACTA at the risingof clock signal CLK in accordance with the state of operation modeinstructing signal CMD; a shifter 131 which transfers active cycleinstructing signal φACTA in accordance with clock signal CLK; aset/reset flip-flop 132 which is set in response to rising of an outputsignal φSH of shifter 131 to set control clock signal φX to H-level; ashifter 133 which transfers control clock signal φX in accordance withclock signal CLK; a one shot pulse generating circuit 134 which producesa one shot pulse signal in response to rising of the output signal ofshifter 133; a delay circuit 135 which delays active cycle instructingsignal φACTA by a predetermined time; and a one shot pulse generatingcircuit 136 which generates a one shot pulse signal in response torising of the output signal of delay circuit 135.

Set/reset flip-flop 132 generates control clock signal φX, and one shotpulse generating circuits 134 and 136 generate transfer instructingsignals φA and φB, respectively. Delay circuit 135 has a delay timeequal to the time required for recovery of the operation power supplyvoltage of active latch circuit AL when active cycle instructing signalφACTA is activated. Owing to provision of delay circuit 135, the signaltransfer from standby latch circuit SL to active latch circuit AL can beperformed upon transition to the active cycle after the power supplyvoltage of active latch circuit AL is sufficiently restored. Therefore,accurate signal latching by the active latch circuit can be ensured.

Shifters 131 and 133 transfer the received signals for predeterminedcycle periods to delay the received signals, respectively. Accordingly,the delay times of shifters 131 and 133 can be set in a unit of half thecycle of clock signal CLK. By adjusting the number of transfer cycles ofshifter 131, the clock cycle period of the active state of control clocksignal φX can be set to either cycle #1 or cycle #3 shown in FIG. 54. Byusing shifter 133, transfer instructing signal φA can be produced afterdeactivation of control clock signal φX. By shifter 133, the activeperiod of control clock signal φX can be adjusted in a unit of half theclock cycle.

This control signal generating portion further includes a set/resetflip-flop 137 which is set in response to rising of active cycleinstructing signal φACTA, and is reset in response to falling oftransfer instructing signal φA. The signal generated from output Q ofset/reset flip-flop 137 is used for the power supply control on activelatch circuit AL and is used, in the case of the hierarchical powersupply structure, as control clock signal φ for the power supply switchtransistor.

In the signal waveform diagram shown in FIG. 54, if the number of clocktransfer cycles of shifter 131 is set to 0, the signal transfer betweenactive latch circuit AL and standby latch circuit SL is performed withclock cycles #1 and #2 being one clock cycle.

[Fourth Modification]

FIG. 56A schematically shows a structure of a fourth modification of theeleventh embodiment of the present invention. In the structure shown inFIG. 56A, a plurality of stages of logic circuits LG#1-LG#n are designedto synchronously operate, and successively execute a processing inaccordance with activating signals φL1-φLn. Latch circuits LT#1-LT#n areprovided corresponding to logic circuits LG#1-LG#n, respectively. Sincelatch circuits LT#1-LT#n have the same structures, FIG. 56A shows onlythe structure of latch circuit LT#i as a representative example. Latchcircuit LT#i includes active latch circuit AL, standby latch circuit SL,transfer gate XF2 for coupling active latch circuit AL to logic circuitLG#i in accordance with control clock signal φXi, and bidirectionaltransfer circuit 105 for transferring signals between active latchcircuit AL and standby latch circuit SL in accordance with transferinstructing signals φAi and φB.

Transfer instructing signal φAi (i=1-n) for controlling the signaltransfer from active latch circuit AL to standby latch circuit SL isproduced for each of latch circuits LT#1-LT#n. When the standby state iscompleted, transfer instructing signal φB for instructing the signaltransfer from standby latch circuit SL to active latch circuit AL isproduced commonly to latch circuits LT#1-LT#n. An operation of thesemiconductor device shown in FIG. 56A will now be described withreference to a signal waveform diagram of FIG. 56B.

When the standby period is completed and the active cycle starts,transfer instructing signal φB is first activated, and each of latchcircuits LT#1-LT#n operate to transfer the signal from standby latchcircuit SL to active latch circuit AL. Prior to this operation, thepower supply for active latch circuit AL, which is controlled during thestandby state, is already recovered. When active cycle instructingsignal φACTA is activated, logic circuits LG#1-LG#n are successivelyactivated in accordance with activation control signals φL1-φLn, toexecute the processing on the signals received from the logic circuitsin the preceding stages, respectively. In each of latch circuitsLT#1-LT#n, when activation control signal φLi for the correspondinglogic circuit is activated in the above processing, control clock signalφXi is activated at a predetermined timing so that transfer gate XF2 isturned on to couple active latch circuit AL to logic circuit LG#i.

In logic circuits LG#1-LG#n, operational processings are executed inaccordance with activation control signals φL1-φLn, and the results ofexecution are latched by associated active latch circuits AL in latchcircuits LT#1-LT#n, respectively. In the next cycle, the signal latchedin active circuit AL is transferred to corresponding standby latchcircuit SL through bidirectional transfer circuit 105. Thus, transferinstructing signals φA1-φAn are activated in the cycle subsequent to theactivation of activation control signals φL1-φLn in logic circuitsLG#1-LG#n, respectively. Therefore, signal transfer from active latchcircuit AL to standby latch circuit SL is performed in the cyclesubsequent to the cycle, in which a corresponding logic circuit LG#ioperates to perform the signal processing. It is not necessary toconsider the signal definition timing in active latch circuit AL and thetiming of signal transfer to standby latch circuit SL based on thesignal processing timing of the logic circuit in each operation cycle,and thus, the signal can be transferred from active latch circuit AL tostandby latch circuit SL with a sufficient margin. A circuit for timingadjustment is not required, and it is possible to reduce the number ofcircuit components as well as the power consumption.

FIG. 57A schematically shows a structure of a portion for generatingtransfer instructing signal φAi shown in FIG. 56A. In FIG. 57A, thetransfer instructing signal generating portion includes: a shifter 140which transfers activation control signal φLi for one clock cycle periodin synchronization with clock signal CLK; and a one shot pulsegenerating circuit 141 which generates a one shot pulse signal inresponse to rising of the output signal of shifter 140. One shot pulsegenerating circuit 141 generates transfer instructing signal φAi. Clocksignal CLK determines the operation cycle of logic circuits LG#1-LG#nshown in FIG. 56A. An operation of the transfer instructing signalgenerating portion shown in FIG. 57A will now be described withreference to a timing chart of FIG. 57B.

When activation control signal φLi is activated in synchronization withthe rising of clock signal CLK, shifter 140 takes in this activationcontrol signal φLi, and outputs the signal thus taken at the next risingof the clock signal CLK. Therefore, during activation of activationcontrol signal φLi in clock cycle #i, a predetermined operationalprocessing is performed in the logic circuit LG#i, and a resultantsignal is transferred and latched into associated active latch circuitAL. Then, activation control signal #Li+1 for logic circuit LG#(i+1) inthe next stage is activated in the next cycle #i+1, and one shot pulsegenerating circuit 141 generates one shot to activate transferinstructing signal φAi in clock cycle #i+1. Accordingly, the signalwhich is latched in clock cycle #i by active latch circuit AL istransferred from active latch circuit AL to standby latch circuit SL inthe next clock cycle #i+1.

Control clock signal φXi is merely required to be activated at anappropriate timing in response to activation control signal φLi.

Activation control signals φL1-φLn can be produced from the shiftregister performing a shifting operation in synchronization with clocksignal CLK when active cycle instructing signal φACTA is activated.

Logic circuits LG#1-LG#n may successively perform the processing in apipeline manner in synchronization with the clock signal CLK, in whichcase a register responsive to the clock signal CLK is arranged ininput/output portion of the pipeline stage. This register performs thesignal transfer between pipeline stages. In synchronization with thissignal transfer between the pipeline stages by the register, a signal istransferred from active latch circuit AL to standby latch circuit SL.Even in such pipeline arrangement, the signal transfer in the next cyclecan be implemented.

[Fifth Modification]

FIG. 58 is a signal waveform diagram representing an operation of afifth modification of the eleventh embodiment according to the presentinvention. In FIG. 58, the semiconductor device has a normal mode ofoperation and a low power consumption mode of operation. For a logiccircuit, the low power consumption mode is a sleep mode in which thelogic circuit stops its operation. For a Dynamic Random Access Memory(DRAM), the low power consumption mode is a self-refresh mode in whichdata refreshing is performed in accordance with internally generatedtiming and address. In the normal mode, the semiconductor deviceexecutes a predetermined processing. As shown in FIG. 58, transferinstructing signal φA is activated upon transition from the normal modeto the low power consumption mode, and the latch signal is transferredfrom active latch circuit AL to standby latch circuit SL. During thisperiod, the device is in a low power consumption entry mode. When thislow power consumption entry mode is completed, the active latch circuitis subject to the power supply control to reduce the gate tunnelcurrent.

When the low power consumption mode is completed, the power supplycontrol for the active latch circuit is first performed. After the powersupply is recovered, transfer instructing signal φB for the active latchcircuit is activated, and the latch signal is transferred from standbylatch circuit SL to active latch circuit AL. When the active period oftransfer instructing signal φB expires and the low power consumptionexit mode is completed, the semiconductor device can execute thepredetermined processing.

In the normal mode, therefore, the MIS transistors having thin gateinsulating films are used for fast operation. In the low powerconsumption mode, the gate tunnel current is reduced, e.g., bycontrolling the power supply voltage of active latch circuit AL, and thepower consumption is reduced. Signal waveforms shown in FIG. 58 can beprovided by substituting the period of the low power consumption modefor the standby period in the waveform diagram of FIG. 48. Therefore,the corresponding control signal generating portion can be used for thecontrol signal generating portion which achieves the waveforms shown inFIG. 58.

According to the eleventh embodiment of the present invention, asdescribed above, a signal, of which the logic level in the standby stateis not determined in advance, is transferred from the active latchcircuit to the standby latch circuit in the standby state, and theactive latch circuit is set to the gate tunnel current reduced state.Thereby, the power consumption due to the gate tunnel current in thestandby state can be suppressed. Upon transition from the standby periodto the active period, the signal latched by the standby latch circuit istransferred to the active latch circuit so that the latched signal canbe accurately restored. Further, fast operations can be achieved by theactive latch circuit during the active period.

Twelfth Embodiment

FIG. 59A shows, by way of example, a structure of a semiconductor deviceaccording to a twelfth embodiment of the present invention. In FIG. 59A,an MIS transistor PTR15, which is turned on when precharge instructingsignal /φPR is active (at L-level), is arranged between the power supplynode and a precharge node 150. N-channel MIS transistors NQ15, NQ16 andNQ17 are arranged in parallel between precharge node 150 and the groundnode. MIS transistors NQ15, NQ16 and NQ17 are supplied on their gateswith input signals IN1, IN2 and IN3, respectively.

Precharge instructing signal /φPR is set to the active state of L-levelin the standby state for precharging the precharge node 150 to powersupply voltage Vcc level. MIS transistor PTR15 for precharge is formedof an ITR transistor for suppressing its gate tunnel current leak. MIStransistors NQ15-NQ17 which are responsive to input signals IN1-IN3,respectively, are formed of MIS transistors having thin gate insulatingfilms, respectively. In the standby state, all input signals IN1-IN3 areat L-level, and MIS transistors NQ15-NQ17 stays in the off state. Anoperation of the semiconductor device shown in FIG. 59A will now bedescribed with reference to an operation waveform diagram shown in FIG.59B.

In the standby state, precharge instructing signal /φPR is at L-level,and precharge node 150 is precharged to the power supply voltage levelby precharging MIS transistor PTR15. All input signals IN1-IN3 are atL-level, and all MIS transistors NQ15-NQ17 maintain the off state.

In the precharged state, MIS transistor PRT15 is on, but the gate tunnelcurrent thereof is sufficiently suppressed because precharging MIStransistor PTR15 is an ITR transistor. MIS transistors NQ15-NQ17 areoff, and the gate tunnel currents hardly occur. MIS transistor PTR15 forprecharging is an ITR transistor, and may have, e.g., a thick gateinsulating film, in which case the threshold voltage thereof is large inabsolute value, and therefore the off-leak current can be reduced.

When the active cycle starts, precharge instructing signal /φPR attainsH-level so that MIS transistor PTR15 for precharging is turned off. MIStransistors NQ15-NQ17 are selectively turned on/off in accordance withthe logical levels of input signals IN1-IN3, respectively. Depending onthe on/off states of MIS transistors NQ15-NQ17, the voltage level onprecharge node 150 during the active period is determined. Fordischarging the precharge node 150 to the ground voltage level, MIStransistors NQ15-NQ17 have the thin gate insulating films, respectively,and can operate fast for discharging precharge node 150 to the groundvoltage level.

Accordingly, by utilizing the ITR transistor for the MIS transistor forprecharging, the gate tunnel current can be suppressed in such a dynamicoperation environment, in which precharge node 150 is precharged to thepredetermined voltage level during the standby period, and the voltagelevel of the precharge node 150 is determined in accordance with theinput signal during the active period, as shown in FIG. 59A.

The standby period and the active period are designated by activationinstructing signal ACT. FIG. 59C shows a general form of thesemiconductor device of the twelfth embodiment of the present invention.In FIG. 59C, the semiconductor device includes MIS transistor PTR15 forprecharging connected between the power supply node and precharge node150, and a logic circuit 155 which drives precharge node 150 inaccordance with input signals (group). Logic circuit 155 is formed ofthin film transistors (Tr) having thin gate insulating films. Logiccircuit 155 has an appropriate structure depending on a use thereof, andis merely required to drive precharge node 150 in accordance with inputsignal IN during the active cycle.

[First Modification]

FIG. 60A shows a structure of a first modification of the twelfthembodiment of the present invention. The structure shown in FIG. 60Aincludes the same components as those shown in FIG. 59A, andadditionally includes an MIS transistor PQ15 for precharging which isturned on when precharge instructing signal /φPR2 is active. MIStransistor PQ15 has a gate insulating film of a small thickness, andtherefore can operate fast. Precharge instructing signal /φPR2 isactivated in the form of a one shot pulse upon transition from theactive period to the standby period. An operation of the semiconductordevice shown in FIG. 60A will now be described with reference to asignal waveform diagram of FIG. 60B.

In the standby state, activation instructing signal ACT is at L-level sothat precharge instructing signal /φPR1 is at L-level, or active. Also,MIS transistor PTR15 for precharging is on, and node 150 is prechargedto power supply voltage Vcc level. Precharge instructing signal /φPR2 isat H-level and inactive, and MIS transistor PQ15 for prechargingmaintains the off state. Since MIS transistor PQ15 for precharge is off,the gate tunnel current does not occur in MIS transistor PQ15 in spiteof the fact that the MIS transistor PQ15 for precharging has a thin gateinsulating film. Input signals IN1-IN3 are at L-level in the standbystate.

When the active period starts, MIS transistor PTR15 for precharging isturned off in accordance with activation instructing signal ACT.Precharge instructing signal /φPR2 maintains H-level. Input signalsIN1-IN3 change in the active period, and MIS transistors NQ15-NQ17 areselectively set to on/off states in accordance with input signalsIN1-IN3, respectively, so that the voltage level of precharge node 150is decided.

When the active period ends, precharge instructing signal /φ PR1 fallsfrom H-level to L-level in response to deactivation of activationinstructing signal ACT, and MIS transistor PTR15 is turned on toprecharge the node 150 to power supply voltage Vcc level. In thisoperation, precharge instructing signal /φPR2 attains L-level for awhile, and MIS transistor PQ15 for precharging is turned on.

The ITR transistor has a large gate tunnel barrier for suppressing agate tunnel current, and has a threshold voltage of a large absolutevalue. Therefore, in the operation of precharging the precharge node 150using MIS transistor PTR15 which is the ITR transistor, a certain timeis required before the voltage level of precharge node 150 is recoveredto power supply voltage Vcc level, and it may be impossible to reduce atime period of the standby period in the case where the standby periodand the active period are alternately repeated at high speed. In view ofthis disadvantage, the MIS transistor, which has a thin gate insulatingfilm and can operate fast, is used for MIS transistor PQ15 forprecharging, so that the precharge node 150 can be restored in voltagelevel fast to power supply voltage Vcc level. Thereby, precharge node150 can be reliably precharged to power supply voltage Vcc level even inthe case where the standby period is short, and reduction in currentconsumption during the standby period and fast operations during theactive period can be both achieved.

FIG. 61 schematically shows a structure of a portion for generating theprecharge instructing signal shown in FIG. 60A. In FIG. 61, theprecharge instructing signal generating portion includes cascadedinverter circuits 155 a and 155 b of two stages for receiving activationinstructing signal ACT, and a one shot pulse generating circuit 156 forgenerating a one shot pulse signal which becomes L-level for apredetermined period in response to the rising of the output signal ofinverter circuit 155 a. Inverter circuit 155 b generates prechargeinstructing signal /φPR1, and one shot pulse generating circuit 156generates precharge instructing signal /φPR2.

Inverter circuits 155 a and 155 b form a buffer circuit, which producesprecharge instructing signal /φPR1 in accordance with activationinstructing signal ACT. When an active period is completed, the outputsignal of inverter circuit 155 a rises to H-level, and responsively oneshot pulse generating circuit 156 produces a one shot pulse signal sothat precharge instructing signal /φPR2 is driven to the active statefor a predetermined period upon transition to the standby period. Thus,the precharge instructing signals /φR1 and /φPR2 can be set to theactive/inactive states in accordance with the operation cycle/period.

[Second Modification]

FIG. 62 is a signal waveform diagram representing an operation of asecond modification of the twelfth embodiment of the present invention.A structure of a semiconductor device used in this modification is thesame as that shown in FIG. 60A. Precharge node 150 is precharged usingthe precharging transistors PTR15 and PQ15, which are turned on inaccordance with precharge instructing signals /φPR1 and /φPR2,respectively. In this signal waveform diagram of FIG. 62, prechargeinstructing signal /φPR2 for turning on the precharging MIS transistorPQ15 having a thin gate insulating film, is activated in a one shotpulse form at the start of the active period. Thus, upon transition fromthe standby period to the active period, precharge instructing signal/φPR2 is kept active for a predetermined period, and MIS transistor PQ15can precharge reliably the precharge node 150 to the predeterminedvoltage level.

When precharge node 150 is to be precharged by MIS transistor PTR15during the standby period, there is no problem even when precharge node150 is not precharged to the predetermined voltage due to inadequatelength of the standby period. In this case, the precharge node 150 canbe reliably precharged to the predetermined voltage level by theprecharge instructing signal /φPR2 at the start of the active period.After completion of the precharging, MIS transistors NQ15-NQ17 areselectively turned on/off in accordance with input signals IN1-IN3.

FIG. 63 schematically shows a structure of a portion generating theprecharge instructing signal shown in FIG. 62. The precharge instructingsignal generating portion shown in FIG. 63 differs from the prechargeinstructing signal generating portion shown in FIG. 61 in the followingpoint. Precharge instructing signal /φPR2 is generated by a one shotpulse generating circuit 157, and is at L-level for a predeterminedperiod in response to rising of activation instructing signal ACT. Atthe start of an active period, precharge instructing signal /φPR2 isdriven to the active state for a predetermined period.

FIG. 64 shows a general structure of the semiconductor devices of thefirst and second modifications of the twelfth embodiment of the presentinvention. In FIG. 64, the semiconductor device includes logic circuit155 for driving precharge node 150 in accordance with input signals(group) IN. Logic circuit 155 includes the MIS transistor (thin film Tr)having a thin gate insulating film as its component. Precharge node 150is precharged to power supply voltage Vcc level by MIS transistors PTR15and PQ15, which receive precharge instructing signals /φPR1 and /φPR2 ontheir gates, respectively. Logic circuit 155 executes a predeterminedlogical processing to drive selectively precharge node 150, similarly tothe structure shown in FIG. 59C.

[Third Modification]

FIG. 65 is a signal waveform diagram representing an operation of athird modification of the twelfth embodiment of the present invention.In the third modification, the semiconductor device has a sleep mode forhalting operations in addition to the standby cycle and the active cyclein the normal operation mode. The structure of the semiconductor deviceis the same as that shown in FIG. 60A, and includes, as the MIStransistors for precharging, MIS transistor PTR15 formed of an ITRtransistor that is turned on in response to precharge instructing signal/φPR1, and MIS transistor PQ15 that is turned on/off in response toprecharge instructing signal /φPR2. An operation of the thirdmodification of the twelfth embodiment of the present invention will nowbe described with reference to a signal waveform diagram of FIG. 65.

When a sleep mode instructing signal SLEEP is at L-level and inactive,the standby cycle and the active cycle are repetitively executed inaccordance with activation instructing signal ACT. When sleep modeinstructing signal SLEEP is at L-level, precharge instructing signal/φPR1 maintains H-level, and responsively MIS transistor PTR15 maintainsthe off state. In the normal operation mode (i.e., when the sleep modeinstructing signal is inactive), precharge instructing signal /φPR2 isdriven to L- or H-level in accordance with activation instructing signalACT. In the standby cycle, precharge instructing signal /φPR2 is atL-level, and MIS transistor PQ15 for precharging is on so that prechargenode 150 is charged fast. In the active cycle, precharge instructingsignal /φPR2 is at H-level, and MIS transistor PQ15 for precharging isoff. In this active cycle, the logic circuit or MIS transistorsNQ15-NQ17 selectively drive precharge node 150 to the ground voltagelevel in accordance with input signals IN1, IN2 and IN3.

When the standby state continues for a predetermined time or more andthe sleep mode instructing signal SLEEP attains H-level to instruct thesleep mode, precharge instructing signal /φPR2 attains H-level, and MIStransistor PQ15 for precharging maintains the off state during the sleepmode period. In response to activation of sleep mode instructing signalSLEEP, precharge instructing signal /φPR1 attains L-level, and MIStransistor PTR15 for precharging is turned on so that precharge node 150is precharged to power supply voltage Vcc level. In the sleep mode, thecurrent consumption is minimized. By turning off MIS transistor PQ15 inthe sleep mode, the gate tunnel current in MIS transistor PQ15 forprecharging is suppressed.

MIS transistor PTR15 is an ITR transistor, and the gate tunnel currentthereof is sufficiently small in the on state. Therefore, it is possibleto suppress the gate tunnel currents in MIS transistors for prechargingPTR15 and PQ15 in the sleep mode. In the normal operation mode,precharge node 150 is precharged using MIS transistor PQ15 whichoperates fast. At the time of transition from the active state to thestandby state, the precharge node can be precharged fast, and fastoperations are allowed. Upon transition to the sleep mode, fastoperation is not required for this transition to the sleep mode.Therefore, there arises no problems even when precharge node 150 isprecharged to a predetermined voltage level using the ITR transistor,and the current consumption in the sleep mode is reduced.

FIG. 66 shows, by way of example, a structure of a portion forgenerating precharge instructing signals /φPR1 and /φPR2 shown in FIG.65. In FIG. 66, the precharge instructing signal generating portionincludes cascaded inverter circuits 160 a and 160 b of two stages forreceiving activation instructing signal ACT, an OR circuit 160 creceiving the output signal of inverter circuit 160 b and sleep modeinstructing signal SLEEP, and an inverter circuit 160 d receiving sleepmode instructing signal SLEEP. OR circuit 160 c generates prechargeinstructing signal /φPR2, and inverter circuit 160 d generates prechargeinstructing signal /φPR1.

Activation instructing signal ACT is produced in accordance with anoperation cycle, based on an externally supplied signal. According tothe structure shown in FIG. 66, OR circuit 160 c operates as a buffercircuit, and inverter circuits 160 a and 160 b also operate as buffercircuits when sleep mode instructing signal SLEEP is at L-level.Therefore, precharge instructing signal /φPR2 changes in accordance withactivation instructing signal ACT. Since sleep mode instructing signalSLEEP is at L-level, precharge instructing signal /φPR1 maintainsH-level.

When sleep mode instructing signal SLEEP attains H-level, prechargeinstructing signal /φPR2 generated from OR circuit 160 c attainsH-level, and precharge instructing signal /φPR1 from inverter circuit160 d attains L-level.

By utilizing the structure shown in FIG. 66, the MIS transistors forprecharging can be selectively used in the normal operation mode and thesleep mode.

[Fourth Modification]

FIG. 67A shows a structure of a fourth modification of the twelfthembodiment of the present invention. In the structure shown in FIG. 67A,an MIS transistor PQ16 which is turned on in accordance with prechargeinstructing signal /φPR is arranged between the power supply node andprecharge node 150. MIS transistor PQ16 has a thin gate insulating film.Precharge node 150 is coupled to MIS transistors NQ15-NQ17, whichreceive internal signals IN1-IN3 on their gates, respectively.

In the semiconductor device shown in FIG. 67A, precharge instructingsignal /φPR is activated in a one shot pulse form at the start of theactive cycle. As shown in FIG. 67B, when activation instructing signalACT rises to H-level, precharge instructing signal /φPR becomes L-levelfor a predetermined period, and MIS transistor PQ16 for precharging isturned on so that precharge node 150 is precharged to the predeterminedvoltage level. MIS transistor PQ16 has a thin gate insulating film, andtherefore precharge node 150 is rapidly precharged to a predeterminedvoltage level in accordance with precharge instructing signal /φPR of aone shot pulse form. After completion of this precharging, prechargenode 150 is selectively discharged to the ground voltage level inaccordance with input signals IN1-IN3.

Even in the case where the gate tunnel current of MIS transistor PQ16 islarge, a period for which this gate tunnel current flows can be reducedby activating precharge instructing signal /φPR of a one shot pulseform. Thereby, the gate tunnel current in the MIS transistor forprecharging can be suppressed.

FIG. 68 schematically shows a structure of a portion for generatingprecharge instructing signal /φPR shown in FIG. 67A. The prechargeinstructing signal generating portion shown in FIG. 68 includes: a modedetecting circuit 162 which detects the operation mode instructed byoperation mode instructing signal CMD, and produces activationinstructing signal ACT; and a one shot pulse generating circuit 164which generates a one shot pulse signal, which in turn becomes L-levelfor a predetermined period in response to the rising of activationinstructing signal ACT generated from mode detecting circuit 162. Oneshot pulse generating circuit 164 generates precharge instructing signal/φPR.

When the active cycle is designated in accordance with operation modeinstructing signal CMD, mode detecting circuit 162 drives activationinstructing signal ACT to the active state (H-level). In response to theactivation (rising) of activation instructing signal ACT, one shot pulsegenerating circuit 164 drives precharge instructing signal /φPR toL-level for a predetermined level. Thereby, precharge node 150 can beprecharged by one shot upon starting of the active cycle.

In the standby state, all the MIS transistors are off so that the gatetunnel currents can be suppressed.

[Fifth Modification]

FIG. 69 shows a structure of a fifth modification of the twelfthembodiment of the present invention. The structure shown in FIG. 69includes the same structure as that shown in FIG. 67A, and furtherincludes an MIS transistor NTR15 which is connected between prechargenode 150 and the ground node, and is selectively turned on in responseto the inverted signal of activation instructing signal ACT. MIStransistor NTR15 is formed of an ITR transistor having a large gatetunnel barrier, and receives activation instructing signal ACT on itsgate via an inverter. Accordingly, MIS transistor NTR15 is turned onwhen the standby period (cycle) starts after completion of the activeperiod (cycle). When the active period starts, precharge instructingsignal /φPR is activated in a one shot pulse form, and precharge node150 is precharged to a predetermined voltage level.

During the standby period, precharge node 150 is held at the groundvoltage level by MIS transistor NTR15, which is an ITR transistor havinga large gate tunnel barrier, Thereby, it is possible to preventprecharge node 150 from electrically floating during the standby period,and a malfunction due to an unstable voltage on precharge node 150 canbe prevented.

During the standby period, other circuits receiving the signal onprecharge node 150 are also in the standby state, and do not operate.Therefore, holding precharge node 150 at the ground voltage level duringthe standby period does not adversely affect the other circuits. Theactive cycle operations start after precharge node 150 is precharged toa predetermined voltage level upon transition to the active period. Byactivating precharge instructing signal /φPR in a one shot pulse form,the other circuits can reliably perform accurate operations inaccordance with the voltage level on precharge node 150.

Since the MIS transistor for preventing the electrical floating has alarge gate tunnel barrier, the gate tunnel current thereof in the onstate is sufficiently suppressed, and the current consumption during thestandby period can be sufficiently reduced.

FIG. 70 schematically shows a general structure of fourth and fifthmodifications of the twelfth embodiment of the present invention. Thestructure shown in FIG. 70 uses a general logic circuit 165 instead ofthe NOR-type logic circuit. Logic circuit 165 includes, as itscomponent, an MIS transistor having a thin gate insulating film. Logiccircuit 165 selectively drives precharge node 150 in accordance withinput signals (group) IN. Other circuits execute predeterminedprocessing in accordance with the voltage level on precharge node 150.

[Sixth Modification]

FIG. 71 shows a structure of a sixth modification of the twelfthembodiment of the present invention. In FIG. 71, MIS transistor PQ16,which is turned on in response to precharge instructing signal /φPR, isarranged between precharge node 150 and the power supply node. An MIStransistor NTR16, which is turned on in response to activation of sleepmode instructing signal SLEEP, is arranged between precharge node 150and the ground node. MIS transistors NQ15, NQ16 and NQ17, which areselectively turned on in accordance with input signals IN1-IN3 and forma logic circuit, are arranged in parallel between precharge node 150 andthe ground node.

MIS transistor NTR16 is an ITR transistor having a large gate tunnelbarrier, and can have sufficiently suppressed gate tunnel current. MIStransistors NQ15-NQ17 are MIS transistors having thin gate insulatingfilms, and perform operations at high speed in accordance with inputsignals IN1-IN3, respectively. An operation of the semiconductor deviceshown in FIG. 71 will now be described with reference to a signalwaveform diagram of FIG. 72.

In the normal mode for processing signals and/or data, sleep modeinstructing signal SLEEP is at L-level, and MIS transistor NTR16maintains the off state. MIS transistor NTR16 is an ITR transistor, andboth the gate tunnel current and the off-leak current are small. In thenormal mode, the active cycle and the standby cycle are repeated. In theactive cycle, precharge instructing signal /φPR repetitively andalternately attains the inactive and active states in accordance withactivation instructing signal ACT. In the active period (cycle),precharge instructing signal /φPR is inactive. In this normal mode ofoperation, precharge node 150 is precharged using MIS transistor PQ16having a thin gate insulating film. In the normal mode of operation,therefore, precharge node 150 can be charged and discharged fast inaccordance with activation instructing signal ACT.

In the sleep mode, sleep mode instructing signal SLEEP attains H-levelso that MIS transistor NTR16 is turned on, and precharge node 150 isfixed to ground voltage level. Precharge instructing signal /φPRmaintains H-level, and MIS transistor PQ16 is turned off.

In this sleep mode, all input signals IN1-IN3 are set to L-level, andall MIS transistors NQ15-NQ17 are off. In the sleep mode in which thelow current consumption is required, therefore, all MIS transistors PQ16and NQ15-NQ17 having the thin gate insulating films are off so that thegate tunnel currents in MIS transistors PQ16 and NQ15-NQ17 can besuppressed.

When the sleep mode ends, sleep mode instructing signal SLEEP returns toL-level, and MIS transistor NTR16 is turned off. When this sleep modeinstructing signal SLEEP attains L-level, precharge instructing signal/φPR attains L-level so that MIS transistor PQ16 is turned on, andprecharges rapidly precharge node 150 to power supply voltage Vcc level.For transition from the sleep mode to the standby state in the normalmode, a period before start of the active cycle is prescribed inspecifications, and a sufficient time is ensured. In transition from thesleep mode to the standby state, therefore, precharge node 150 can bereliably precharged to a predetermined voltage level using MIStransistor PQ16 for precharging.

FIG. 73 schematically shows a structure of a portion generating theprecharge instructing signal and the sleep mode instructing signal shownin FIG. 71. The control signal generating portion shown in FIG. 73includes a mode detecting circuit 170 which receives externally suppliedoperation mode instructing signal CMD, and selectively activatesactivation instructing signal ACT and sleep mode instructing signalSLEEP in accordance with the designated operation mode, cascadedinverter circuits 171 and 172 of two stages for receiving activationinstructing signal ACT from mode detecting circuit 170, and an ORcircuit 173 which receives the output signal of inverter circuit 172 andsleep mode instructing signal SLEEP, and produces precharge instructingsignal /φPR.

When operation mode instructing signal CMD designates the active cycle,activation instructing signal ACT attains H-level. Thereby, prechargeinstructing signal /φPR becomes active when sleep mode instructingsignal SLEEP is at L-level. When sleep mode instructing signal SLEEP isat L-level, precharge instructing signal /φPR is produced in accordancewith activation instructing signal ACT.

When sleep mode instructing signal SLEEP attains the active state ofH-level, precharge instructing signal /φPR generated from OR circuit 173is fixed to H-level. Thereby, the activation manner of prechargeinstructing signal /φPR can be switched in accordance with the operationmode. In this sixth modification, precharge instructing signal /φPR maybe generated in the form of a one shot pulse.

The semiconductor device of the sixth modification of the twelfthembodiment of the present invention shown in FIG. 71 has the generalform which is substantially the same as that shown in FIG. 70.

According to the twelfth embodiment of the present invention, asdescribed above, the MIS transistor having a thin gate insulating filmis used for assisting the precharge operation in the case where the MIStransistor having a large gate tunnel barrier is used as the MIStransistor for precharging. In the case where the MIS transistor havinga thin gate insulating film is utilized as the MIS transistor forprecharging, this MIS transistor for precharging is continuously keptoff, or is kept on for only a short time in the mode requiring reductionin current consumption. Thereby, the gate tunnel current can besuppressed, without adversely affecting the operation speed, in thestandby state in which reduction in current consumption is required.

Thirteenth Embodiment

FIG. 74A schematically shows a structure of a main portion of asemiconductor device according to a thirteenth embodiment of the presentinvention. The semiconductor device shown in FIG. 74A is a dynamicsemiconductor memory device (DRAM), and includes a memory cell array 200having a plurality of memory cells arranged in rows and columns. Thememory cells, which are arranged in rows and columns in memory cellarray 200, are dynamic memory cells, and are required to refresh storagedata in predetermined intervals.

This semiconductor device further includes: a row-address-relatedcircuit 203 for producing a row address designating a row in memory cellarray 200; a row-related circuit block 204 including a word line drivecircuit for driving a word line arranged corresponding to the addressedrow in memory cell array 200 to the selected state in accordance withthe row address received from row-address-related circuit 203, and asense-related circuit for sensing and amplifying data of the memorycells connected to the selected row; and a column-related circuit block205 including peripheral circuitry for performing column selection andinput/output of data.

Row-address-related circuit 203 includes a row address buffer whichreceives an applied row address and generates an internal row address, arow decode circuit for decoding the row address received from the rowaddress buffer, and a row-address-related control circuit forcontrolling operations of the row address buffer and the row decodecircuit.

Row-related circuit block 204 including the word line drive circuit andthe sense-related circuit further includes a row-related control circuitfor controlling operations of the word line drive circuit and thesense-related circuit. Row-related circuit block 204 further includescircuits such as a circuit for controlling precharge/equalize circuits,which are arranged corresponding to the columns in memory cell array 200for precharging the columns to a predetermined intermediate voltagelevel, and a bit line isolation gate control circuit for controllingconduction/non-conduction of bit line isolation gates in a shared senseamplifier structure, if employed. Column-related circuit block 205including other peripheral circuits operates when a column selectioninstruction is applied.

The semiconductor device further includes a refresh address counter 201which produces a refresh address designating a row to be refreshed inthe refresh (self-refresh) mode, and a refresh timer 202 which issues arefresh request in predetermined intervals in the self-refresh mode. Therefresh address generated from refresh address counter 201 is applied torow-address-related circuit 203. The refresh request signal issued fromrefresh timer 202 is applied to row-address-related circuit 203 androw-related circuit block 204 for controlling operations thereof in therefresh mode.

The self-refresh mode includes a refresh active period for actuallyperforming the refresh and a refresh standby period for waiting issuanceof the refresh request. The normal operation mode likewise includes theactive cycle and the standby cycle. The self-refresh mode usuallyaccompanies the low power consumption mode, and it is preferable tominimize the current consumption in this self-refresh mode. In view ofthis, refresh address counter 201 and refresh timer 202 operating in therefresh mode are formed of ITR transistors having large gate tunnelbarriers, such as thick film transistors each having a thick gateinsulating film.

In contrast, row-address-related circuit 203, row-related circuit block204 and column-related circuit block 205 are required to operate in thenormal operation mode, and are required to have fast operation ability.Therefore, row-address-related circuit 203, row-related circuit block204 and column-related circuit block 205 are formed of MIS transistorseach having a thin gate insulating film.

Even if refresh address counter 201 and refresh timer 202 are formed ofITR transistors having large gate tunnel barriers, there substantiallycauses no problem because these components are not required to operatefast in the self-refresh mode. When row-address related circuit 203,row-related circuit block 204 and column-related circuit block 205 arein the refresh standby state during the self-refresh mode, the gatetunnel currents are suppressed basically by the structures of the firstand third embodiments already described. Power supply to these circuitand blocks may be stopped. Accordingly, the current consumption in theself-refresh mode can be reduced without impairing the fast operationability in the normal operation mode.

In FIG. 74A, the operation for suppressing the gate tunnel current,e.g., by stopping supply of the power supply voltage is executed forcolumn-related circuit block 205 including other peripheral circuits inthe self-refresh mode. As for row-address-related circuit 203 androw-related circuit block 204 related to the row selection, themechanisms for suppressing the gate tunnel current thereof areselectively activated in accordance with the refresh standby state andthe refresh active state in the self-refresh mode.

FIG. 74B shows a structure of one stage in refresh address counter 201shown in FIG. 74A. The structure shown in FIG. 74B is employed by arequired number of stages, of which number depends on the number ofrefresh address bits. In FIG. 74B, refresh address counter 201 includesclocked inverters 201 a and 201 b which are selectively activated inresponse to a refresh address bit /Qi−1, to invert a signal appliedthereto during the active state, an inverter 201 c which inverts andapplies the output signal of clocked inverter 201 b to the input ofclocked inverter 201 a, an inverter latch 201 d which latches the outputof clocked inverter 201 a, and an inverter latch 201 e which latches theoutput signal of clocked inverter 201 b. Clocked inverter 201 bgenerates refresh address bit Qi. All of these inverters are formed ofITR transistors, e.g., having thick gate insulating films. An operationof the refresh address counter shown in FIG. 74B will now be brieflydescribed.

When bit /Qi−1 is at H-level, clocked inverter 201 a is in the outputhigh-impedance state, and clocked inverter 201 b is activated to invertthe signal latched by inverter latch 201 d for producing bit Qi. Sincebit Qi is latched by inverter latch 201 d, bit Qi changes when bit /Qi−1attains H-level. Thus, the logical level of higher bit Qi changes whenlower bit Qi−1 changes from H-level to L-level. While bit /Q-i is atL-level, clocked inverter 201 b is in the output high-impedance state,and bit Qi does not change. The count circuit can be formed of anystructure, provided that the logical level of the higher bit changeswhen the lower bit changes from H-level to L-level and a carry from thelower bit generates.

The refresh timer may have a circuit structure similar to a conventionalstructure utilizing a charge/discharge time of a capacitor.

[First Modification]

FIG. 75 schematically shows a structure of a first modification of thethirteenth embodiment of the present invention. In FIG. 75, arow-address-related circuit 206 and a row-related circuit block 207,which are activated in the refresh mode, are arranged corresponding torow-address-related circuit 203 and row-related circuit block 204,respectively. These row-related circuit block 207 androw-address-related circuit 206 operate only in the refresh mode, andinclude, as their components, ITR transistors which are, e.g., thickfilm transistors having thick gate insulating films, respectively.

Row-address-related circuit 203 and row-related circuit block 204include, as their components, MIS transistors having thin gateinsulating films, respectively, and execute a row selecting operation onmemory cell array 200 in the normal operation mode. In the refresh mode(self-refresh mode), row-address-related circuit 206 and row-relatedcircuit block 207 execute the row selecting operation on memory cellarray 200. Power supply voltages and others of row-address-relatedcircuit 203 and row-related circuit block 204 are controlled to suppressthe gate tunnel currents in the refresh mode.

In column-related circuit block 205 including other peripheral circuits,the gate tunnel current reducing mechanism is likewise activated in therefresh mode and the standby state.

In the decode circuit or the like of row-address-related circuit 206employing a thick film transistor, measures such as increasing of thepower supply voltage, as needed, are taken so as to sufficientlysuppress the influence by the threshold voltage of the thick filmtransistor for ensuring accurate operations.

As described above, the row-selection-related circuit which operates inthe normal operation mode is arranged independently of therow-selection-related circuit which operates in the self-refresh mode.Thereby, the current consumption due to the gate tunnel current in theself-refresh mode can be reduced without impairing the operationcharacteristics in the normal operation mode.

The sense-related circuits included in row-related circuit blocks 204and 207 are formed of a circuit block, which controls the operations ofsense amplifiers arranged in memory array 200. For the sense amplifiers,it is not necessary to provide the sense amplifier circuit for thenormal operation mode and the sense amplifier circuit for the refreshmode independently of each other. This is because cross-coupled MIStransistors forming the sense amplifier circuit, are all off in thestandby state. However, a sense amplifier activating transistor foractivating the sense amplifier circuit in the self-refresh mode may beemployed independently of that operating in the normal operation mode.This sense amplifier activating transistor for the refresh mode has onlyto be formed of an MIS transistor having a large gate tunnel barrier andsmall current drive capability, so as to reduce the average DC currentduring operation of the sense amplifier circuit. Thus, the DC currentconsumption in the self-refresh mode can be reduced.

FIG. 76 schematically shows a structure of a control portion for thestructure shown in FIG. 75. The control portion in FIG. 76 includes arefresh mode detecting circuit 210 for detecting that the self-refreshmode is designated in accordance with operation mode instructing signalCMD, a multiplexer (MUX) 214 for selecting one of the outputs ofrow-related circuit blocks 207 and 204 in accordance with a refresh modeinstructing signal SRF generated from refresh mode detecting circuit210, and a gate tunnel current reducing mechanism 212 for performingpower control and others of row-address-related circuit 203 androw-related circuit block 204 in accordance with refresh modeinstructing signal SRF. Refresh mode detecting circuit 210 includes, asits components, MIS transistors each having a large gate tunnel barrier.

When the refresh mode is designated by activation of refresh modeinstructing signal SRF, gate tunnel current reducing mechanism 212performs the power supply control and others on row-address-relatedcircuit 203 and row-related circuit block 204 so that the gate tunnelcurrent therein is reduced. Gate tunnel current reducing mechanism 212may be merely configured to interrupt the supply of the power supplyvoltage to row-address-related circuit 203 and row-related circuit block204.

In the refresh mode, multiplexer 214 selects and apply the outputsignals of row-related circuit block 207 including the word line drivecircuit and the sense-related circuit to memory cell array 200.Self-refresh mode instructing signal SRF generated from refresh modedetecting circuit 210 is applied to refresh timer 202 and column-relatedcircuit block 205. A gate tunnel current reducing mechanisms is likewiseprovided for the column-related circuit block so that the power supplyor the bias of column-related circuit block 205 is so controlled as toreduce the tunnel current in accordance with refresh mode instructingsignal SRF. Refresh timer 202 issues a refresh request at predeterminedintervals while refresh mode instructing signal SRF is active.

Row-address-related circuit 206 and row-related circuit block 207 may beconfigured to be selectively activated in accordance with refresh modedetection signal SRF generated from refresh mode detecting circuit 210,and to have supply of the power supply voltage stopped when the normaloperation mode is designated and refresh mode instructing signal SRF isinactive.

[Second Modification]

FIG. 77 schematically shows a structure of a second modification of thethirteenth embodiment of the present invention. The structure shown inFIG. 77 differs in the following point from the structure shown in FIG.74. A MIS transistor PTR20 receiving, on its gate, a prechargeinstructing signal /φPWR1 is provided for row-address-related circuit203 and row-related circuit block 204. Also, an MIS transistor PTR22,which is selectively turned on in response to a precharge instructingsignal /φPWR2, is provided as a power supply control transistor forcolumn-related circuit 205.

MIS transistors PTR20 and PTR22 are ITR transistors having large gatetunnel barriers. Row-address-related circuit 203 and circuit 204 (i.e.,word line drive and sense-related circuit 204) include MIS transistorseach having a gate insulating film of a minimized thickness ascomponents thereof. Column-related circuit 205 including otherperipheral circuits is formed of MIS transistors having thin gateinsulating films. Structures other than the above are the substantiallysame as those shown in FIG. 74. An operation of the semiconductor deviceshown in FIG. 77 will now be described with reference to a signalwaveform diagram of FIG. 78.

In the normal operation mode, refresh mode instructing signal SRF is atL-level. In this state, both power supply control signals /φPWR1 and/φPWR2 are at L-level, and power supply transistors PRT20 and PTR22 areon. Therefore, row-address-related circuit 203, row-related circuit 204and column-related circuit 205 operate fast in accordance with theapplied signals.

When the refresh mode is designated, refresh mode instructing signal SRFrises to H-level. Responsively, power supply control signal /φPWR2attains H-level, and power supply transistor PRT22 is turned off.Thereby, supply of the power supply voltage to column-related circuit205 stops so that current consumption of column-related circuit (otherperipheral circuits) 205 is reduced. When refresh mode instructingsignal SRF is at H-level, a refresh activating signal RFACT, which isproduced in accordance with a refresh request issued from refresh timer202, is activated, and power supply control signal /φPWR1 attainsL-level. In this refresh mode, when refresh activating signal RFACT isat L-level, or inactive, the semiconductor device is placed in thestandby state. In this standby state, precharge instructing signal/φPWR1 is at H-level. In the refresh mode, therefore, power supplytransistor PTR20 is on while this refresh operation (row selectingoperation) is being performed. In the standby state, supply of the powersupply voltage to row-address-related circuit 203 and row-relatedcircuit (word line drive and sense-related circuit) 204 stops. Thus, thecurrent consumption in the refresh mode can be reduced.

In the structure shown in FIG. 77, power supply transistors PTR20 andPTR22 control the supply of power supply voltage. However, these powersupply transistors PTR20 and PTR22 may be replaced with the gate tunnelcurrent suppressing mechanism of any of the first or third embodiment,in which a deep well bias is employed, the polarity of power supplyvoltage is switched, or a sub-power supply line is isolated in thehierarchical power supply structure. The gate tunnel current reducingmechanism may be configured to be activated when power supply controlsignals /φPWR1 and /φPWR2 are inactive.

FIG. 79 shows a structure of a portion generating the control signalsshown in FIG. 78. Refresh mode instructing signal SRF is produced frommode detecting circuit 210, which detects the designation of the refreshmode in accordance with operation mode instructing signal CMD. Buffercircuit 220 buffers this refresh mode instructing signal SRF to producepower supply control signal /φPWR2. In FIG. 79, buffer circuit 220includes, e.g., cascaded inverters of two stages.

Refresh timer 202 issues refresh request signal REFQ at predeterminedintervals when refresh mode instructing signal SRF is at H-level andactive. One shot pulse generating circuit 222 produces a one shot pulsehaving a predetermined time width in accordance with refresh requestsignal REFQ. The one shot pulse generated from one shot pulse generatingcircuit 222 is applied as refresh activating signal RFACT to circuitblocks 203 and 204. While refresh activating signal RFACT is active, rowselection as well as sensing, amplification and restoring of data areperformed.

This control signal generating portion includes an NAND circuit 224which receives refresh mode instructing signal SRF and refreshactivating signal RFACT, and an AND circuit 226 which receives theoutput signal of NAND circuit 224 and refresh mode instructing signalSRF. AND circuit 226 generates power supply control signal /φPWR1.

In the normal operation mode, refresh mode instructing signal SRF is atL-level, and power supply control signal /φPWR1 maintains L-level. Whenrefresh mode instructing signal SRF is at H-level, AND circuit 226operates as a buffer circuit, and NAND circuit 224 operates as aninverter circuit. In the refresh mode, therefore, power supply controlsignal /φPWR1 is produced as an inverted signal of refresh activatingsignal RFACT.

Refresh activating signal RFACT may be produced but from a set/resetflip-flop, which is set in accordance with refresh request signal REFQ,and is reset upon elapsing of a predetermined time from generation ofthe sense amplifier activating signal, rather than one shot pulsegenerating circuit 222.

This control signal generating circuit includes, as its components, MIStransistors having large gate tunnel barriers. In the self-refresh mode,fast operation performance is not required. In the normal mode, powersupply control signals /φPWR1 and /φPWR2 are both fixed to L-level, andtherefore fast operation feature is not impeded at all in the normalmode so that no problem occurs.

Control signals /PWR1 and /PWR2 may be both at L-level in the normalmode. Further, in the refresh mode, control signal /PWR1 may be activefor the refresh active state, and may be inactive for the refreshstandby state, and control signal /PWR2 may be inactive during therefresh mode. Any structure can be used for producing control signals/PWR1 and PWR2, as far as the above signal conditions are satisfied.

[Third Modification]

FIG. 80 schematically shows a structure of a third modification of thethirteenth embodiment of the present invention. In FIG. 80, asemiconductor device 250 includes a DRAM section and a logic section.This semiconductor device is a system LSI including a logic and a DRAMsection mounted on a common semiconductor chip. The DRAM sectionincludes memory cell array 200, row-address-related circuit 203, wordline drive and sense-related circuit (row-related circuit) 204,column-related circuit 205 including other peripheral circuits, refreshaddress counter 201 and refresh timer 202.

Except for refresh address counter 201 and refresh timer 202, this DRAMsection uses, as circuit components, logic transistors (MIS transistors)which have thin gate insulating films and are the same as MIStransistors used in the logic section. Refresh address counter 201 andrefresh timer 202 are formed of MIS transistors (ITR transistors) havinglarge gate tunnel barriers.

This system LSI can operate in several kinds of operation modes, and canoperate in the active/standby cycles during the normal access cycle aswell as in a low-current-consumption standby state which is called as asleep mode. In the sleep mode, the logic section stops its operation. Inthe normal access cycle, current consumption of tens of milliamperes isallowed in the logic section including the logic circuit even during astandby state internally.

In the sleep mode, the following operations are performed. The logicsection is isolated from its external power supply, for achieving thelow power consumption of the logic section. In the DRAM section, storeddata is held in memory cell array 200 with a minimum currentconsumption. Accordingly, the self-refresh operation in the sleep modeis performed with a necessary minimum power.

Power supply transistor PTR20 is provided for row-address-relatedcircuit 203 and row-related circuit 204. Power supply transistor PTR22is provided for other periphery circuits (column-related circuit 205).Power supply transistors PTR20 and PTR22 are ITR transistors,respectively, and receive a memory power supply voltage Vcd. In thelogic section, power supply transistor PTR24 formed of the ITRtransistor is arranged as the power supply transistor. Power supplytransistor PTR24 is controlled with power supply control signal /φPWR2.

In the normal operation mode, all power supply transistors PTR20, PTR22and PTR24 are off. The operation waveforms of power supply controlsignals /φPWR1 and /φPWR2 are the same as those shown in FIG. 78. Whenthe sleep mode is set and the DRAM section enters the self-refresh mode,the power supply voltage is supplied to row-address-related circuit 203and word line drive and sense-related circuit (row-related circuit 204)or the tunnel leak current reducing mechanism is kept inactive onlywhile the refresh is performed in accordance with power supply controlsignal /φPWR1. In the standby state during the sleep mode, power supplycontrol signal /φPWR1 is set to activate the tunnel current reducingmechanism. For column-related circuit 205 including other peripheralcircuits, power supply control signal /φPWR2 is set to turn off powersupply transistor PTR22 so that supply of the power supply voltage tocolumn-related circuit 205 stops.

During the sleep mode, power supply transistor PTR24 is turned off inaccordance with power supply control signal /φPWR2. Therefore, the powerconsumption of the system LSI in the sleep mode can be reduced.

For the logic section, power supply transistor PTR24 receives a logicpower supply voltage Vcl. In this logic section, however, as analternative to power supply transistor PTR24, supply of logic powersupply voltage Vcl may be externally stopped, and logic power supplyvoltage Vcl may be discharged to the ground voltage level internally. Ineither case, it is merely required that the gate tunnel current reducingmechanisms are active in the logic section and the DRAM section whenpower supply control signals /φPWR1 and /φPWR2 are inactive.

In the structure of the system LSI shown in FIG. 80, the circuit whichis responsive to power supply control signals /φPWR1 and /φPWR2 in theDRAM section may be the gate tunnel current reducing mechanism, whichhas any of the structures in the foregoing embodiments.

FIG. 81 schematically shows a structure of a portion for generating thepower supply control signals shown in FIG. 80. In FIG. 81, a powersupply control signal generating portion includes a sleep mode detectingcircuit 260 which decodes an instruction OPC applied, e.g., from asystem controller, and detects entry and exit of the sleep mode, and amode detecting circuit 262 which receives a self-refresh mode entrycommand SRFin and a self-refresh mode exit signal SRFout from sleep modedetecting circuit 260, and produces self-refresh mode instructing signalSRF. Mode detecting circuit 262 receives a memory power supply voltageVcd, and preferably includes an ITR transistor as its component.Self-refresh instructing signal SRF is applied to the circuit shown inFIG. 79 for producing power supply control signals /φPWR1 and /φPWR2.

Sleep mode detecting circuit 260 is provided in the logic section, andreceives logic power supply voltage Vcl as its operation power supplyvoltage. In the logic section, when the sleep mode designation isdetected, supply of logic power supply voltage Vcl is cut off uponelapsing of a predetermined time after issuance of sleep mode entrycommand SRFin. In releasing the sleep mode, the system controllerapplies a sleep mode exit instruction as instruction OPC after logicpower supply voltage Vcl is supplied. In the sleep mode, therefore,sleep mode detecting circuit 260 operates accurately to generateself-refresh entry command SRFin and self-refresh exit command SRFout tomode detecting circuit 262 even when supply of power supply voltage Vclstops in the logic section.

Sleep mode detecting circuit 260 may alternatively be configured toreceive memory power supply voltage Vcd. In this case, sleep modedetecting circuit 260 always monitors instruction OPC which is appliedfrom the system controller.

Memory power supply voltage Vcd is always supplied to refresh addresscounter 201 and refresh timer 202.

[Fourth Modification]

FIG. 82 schematically shows a structure of a fourth modification of thethirteenth embodiment of the present invention. In FIG. 82,semiconductor device 250 is a system LSI, and includes a DRAM sectionand a logic section mounted on a common chip. In the DRAM section, gatetunnel current reducing mechanisms 270 and 272, which are selectivelyactivated in response to power supply control signal /φPWR1, areprovided for row-address-related circuit 203 as well as word line driveand sense-related circuit (row-related circuit) 204, respectively. Forother peripheral circuits (column-related circuit 205), a gate tunnelcurrent reducing mechanism 274 which is selectively activated inresponse to power supply control signal /φPWR2 is provided. Instead ofthe configuration of stopping the power supply, gate tunnel currentreducing mechanisms 270, 272 and 274 may be configured into any of thestructures (well bias changing structure, hierarchical power supplystructure, source voltage changing structure and others) in theembodiments already described.

The logic section is supplied with logic power supply voltage Vcl. Logicpower supply voltage Vcl for the logic section is not supplied in thesleep mode. For the DRAM section, memory power supply voltage Vcd isalways supplied. These power supply control signals /φPWR1 and /PWR2 areproduced from the control signal generating portion shown in FIG. 81. Byutilizing the structure shown in FIG. 82, it is likewise possible toreduce both the power consumption of the DRAM section and the powerconsumption of the logic section in the sleep mode associated with thelow power consumption even in the case where the DRAM section is alwayssupplied with memory power supply voltage Vcd.

According to the thirteenth embodiment of the present invention, asdescribed above, the circuitry related only to the refresh operation isformed of the ITR transistors. For the other circuitry portion, the gatetunnel current reducing mechanism is activated in the standby stateassociated with the low current consumption. Therefore, the currentconsumption can be reduced in the standby state associated with the lowpower consumption without impairing the fast operation feature.

Fourteenth Embodiment

FIG. 83 schematically shows a whole structure of a semiconductor deviceaccording to a fourteenth embodiment of the present invention. In FIG.83, a semiconductor device 300 includes a plurality of internal circuitsLK#1-LK#3, a scan path 302 including a plurality of scan registers(flip-flops) F1-F7 provided for internal nodes of internal circuitsLK#1-LK#3, and a test and power supply control circuit 304 forcontrolling the power supplies to internal circuits LK#1-LK#3 and scanpath 302, and also controlling a test.

Scan registers F1-F7 of scan path 302 are connected in series between ascan data input terminal 309 a and a scan data output terminal 309 b. Ina test operation, scan data SCin is successively transferred and latchedvia scan path 302 under the control of test and power supply controlcircuit 304. Subsequently, internal circuits LK#1-LK#3 operate, and theresults of operation thereof are latched by scan registers F1-F7 again.Thereafter, the data latched by scan registers F1-F7 is successivelyoutput via scan path 302 from a scan data output terminal 309 b as scandata SCout.

In the normal operation, scan registers F1-F7 operate as throughcircuits, and transfer the signals on the corresponding internal nodesto the subsequent internal circuits. In the normal operation, therefore,the signal/data are input via a normal input terminal group 306, andinternal circuits LK#1-LK#3 execute predetermined operations. In thisnormal operation, scan path 302 transfers the signals on the respectiveinternal nodes to the corresponding nodes of the internal circuits atthe following stages. The processing result of internal circuit LK#3 isoutput via a normal signal output terminal group 308.

Provision of scan path 302 in semiconductor device 300 facilitates thetest of the semiconductor device. More specifically, by providing scanpath 302, internal circuits LK#1-LK#3 surrounded by scan registers F1-F7can be individually and independently tested. In the test operation,internal circuits LK#1-LK#3 in semiconductor device 300 can be accesseddirectly through external terminal group 306 or via scan path 302.Thereby, controllability and observability of the internal nodes ofsemiconductor device 300 can be improved.

For the test of, e.g., internal circuit LK#2, a test pattern is set viascan data input terminal 309 a in scan registers F1-F3 provided at theinput nodes of internal circuit LK#2. Internal circuit LK#2 operates,and a result of this operation is taken into scan registers F7 and F6provided at the output nodes of internal circuit LK#2. Then, the resultis taken out as scan-out data SCout via scan path 302 and scan dataoutput terminal 309 b. By observing scan-out data SCout, the operationstate of internal circuit LK#2 can be observed.

The shift and latch operations in scan path 302 are controlled by testand power supply control circuit 304. Test and power supply controlcircuit 304 controls the power supply to internal circuits LK#1-LK#3 andscan path 302. Internal circuits LK#1-LK#3 are supplied with powersupply voltage VCL. Scan registers F1-F7 of scan path 302 are suppliedwith a power supply voltage VCS. In the standby state, e.g., during thesleep mode, supply of power supply voltage VCL to internal circuitsLK#1-LK#3 stops. Scan registers F1-F7 of scan path 302 latch the outputnodes of internal circuits LK#1 and LK#2 before this stop of the powersupply. San registers F1-F7 of scan path 302 are provided with transfergates (logic gates) for switching the operation between the testoperation and the normal operation. By utilizing the logic gate(transfer gate), transfer and latch of the signal are performed.Thereby, current consumption of semiconductor device 300 is reduced inthe standby state, e.g., during the sleep mode.

FIG. 84 schematically shows a structure of test and power supply controlcircuit 304 shown in FIG. 83. In FIG. 84, test and power supply controlcircuit 304 includes: a test control circuit 312 which produces anoperation mode instructing signal MODE and a shift clock signal SFT forcontrolling the shift operation of scan path 302 in accordance withoperation mode instruction OPC; a mode detecting circuit 313 whichdetects the designation of the standby mode in response to operationmode instruction OPC; and a power supply transistor 314 which is turnedoff in response to a standby instructing signal φST received from modedetecting circuit 313, to isolate main power supply line 311 from aninternal circuit power supply line 315.

Test control circuit 312 and mode detecting circuit 313 are externallysupplied with a power supply voltage VEX through power supply nodes 310a and 310 b, respectively. Main power supply line 311 is coupled to ascan path power supply line 316 and scan path power supply voltage VCScorresponding to external power supply voltage VEX is always supplied toscan path 302.

Test control circuit 312, mode detecting circuit 313 and power supplytransistor 314 are formed of MIS transistors having large gate tunnelbarriers. In the test operation utilizing scan path 302, fast operationperformance is not significantly required for transferring signalsthrough scan path 302, and therefore even with test control circuit 312formed of the MIS transistors having large gate tunnel barriers,substantially no problem is caused.

FIG. 85 schematically shows a structure of scan registers F1-F7 includedin scan path 302 shown in FIG. 83. Scan registers F1-F7 have the samestructures, and FIG. 85 shows, by way of example, only one of them asscan register F#.

In FIG. 85, scan register F# includes: a multiplexer (MUX) 320 whichselects one of a shift-in signal SI and an internal signal DI inaccordance with shift mode instructing signal SFMD; a flip-flop (shiftregister) 321 which takes in and transfers a signal applied frommultiplexer 320 in accordance with shift clock signal SFT; a throughlatch 322 which takes in the output signal of flip-flop 321 inaccordance with an update instructing signal UPDATE; and a multiplexer(MUX) 323 which selects and outputs either internal signal DI or theoutput signal of through latch 322 in accordance with mode instructingsignal MODE.

Shift mode instructing signal SFMD, mode instructing signal MODE, shiftclock signal SFT and update instructing signal UPDATE are produced bytest control circuit 312 shown in FIG. 84.

Shift mode instructing signal SFMD designates the signal to be selectedbetween internally applied signal DI and the signal (scan-in signal) SIshifted out from the scan register at a preceding stage in the scanpath, in the scan test mode. Flip-flop 321 forms a shift register inscan path 302, and shifts the signal received from multiplexer 320 inaccordance with shift clock signal SFT. Flip-flop 321 produces ashift-out signal SO for the scan register at the subsequent stage inscan path 302.

Through latch 322 enters a through state for passing the output signalof flip-flop 321 therethrough when update instructing signal UPDATEbecomes active. When update instructing signal UPDATE is inactive,through latch 322 enters the latching state, and merely latches outputsignal SO of flip-flop 321 with passage of the output signal offlip-flop 321 inhibited.

Multiplexer 323 selects internal signal DI when mode instructing signalMODE designates the normal operation mode, and selects the signalapplied from through latch 322 when the test operation mode isdesignated.

In transition to the standby state, scan register F# is utilized, andmultiplexer 320 and flip-flop 321 are operated to latch internal signalDI in flip-flop 321. In this standby state, flip-flop 321 holds thesignal on an internal node of semiconductor device 300 even when thepower supply to internal circuits LK#1-LK#3 is cut off in the standbystate.

After completion of the standby state, the signal held in flip-flop 321is applied to the internal circuit by setting through latch 322 into thethrough state and multiplexer 323 to select the signal applied fromthrough latch 322. Thereby, internal circuits LK#1-LK#3 can return fastto the original state. In the structure of the scan path shown in FIG.83, internal circuit LK#1 is not provided at its input node with aflip-flop. However, the input node of internal circuit LK#1 is coupledto normal signal input terminal group 306, and the normal input terminalgroup 306 can be recovered to the original state (by an external device)immediately after completion of the standby state so that the state ofinternal circuit LK#1 can be restored to the original state.

An operation of the circuits shown in FIGS. 83-85 will now be describedwith reference to a timing chart of FIG. 86.

When operation mode instruct OPC instructs the standby state associatedwith a low power consumption, test control circuit 312 first activatesshift clock signal SFT. In the normal operation mode, shift modeinstructing signal SFMD is set to, e.g., L-level, and multiplexer (MUX)320 selects internal signal DI sent from the internal circuit at thepreceding stage. Therefore, flip-flop 321 takes in the internal signalapplied through multiplexer 320 in accordance with shift clock signalSFT. When shift clock signal SFT becomes inactive, and flip-flop 321latches internal signal DI, mode detecting circuit 313 drives standbyinstructing signal φST to H-level, to turn off power supply transistor314. Thus, the standby entry mode is completed, and the power supply tointernal circuits LK#1-LK#3 stop to reduce the leak currents due to gatetunnel currents in internal circuits LK#1-LK#3.

When the standby state is completed, operation mode instruction OPCchanges, e.g., to L-level for starting the normal operation mode (normalmode). In response to the standby completion instruction (falling) ofoperation mode instruction OPC, standby instructing signal φST from modedetecting circuit 313 attains L-level, and responsively internal circuitpower supply line 315 is coupled to main power supply line 311, so thatpower supply voltage VCL is supplied to internal circuits LK#1-LK#3.Then, test control circuit 312 sets mode instructing signal MODE, e.g.,to H-level in response to the standby completion instruction (falling)of operation mode instruction OPC after establishment of supply of thepower supply voltage to internal circuits LK#1-LK#3. Multiplexer 323selects the output signal of through latch 322. At this point in time,update instructing signal UPDATE applied from test control circuit 312attains H-level, and responsively through latch 322 attains the throughstate, so that the internal signal latched by flip-flop 321 is appliedto multiplexer 323. Therefore, the signal which was applied at the timeof transition to the standby state is applied to the internal circuit inthe subsequent stage. Thus, the standby exit mode is completed, and thesemiconductor device returns to the state of executing the predeterminedoperation in the next normal operation mode.

FIG. 84 does not shows a response relationship between signals of testcontrol circuit 312 and those of mode detecting circuit 313. Controlsignals for them have only to be generated with the delay times takeninto consideration, or the control signals may be generated inaccordance with a predetermined operation sequence based on the responserelationship between the correlated control signals. Through latch 322is configured in view of a boundary scan mode, which is standardized inJTAG (Joint Test Action Group) as described later, and may not beprovided.

FIG. 87 shows, by way of example, structures of test control circuit 312and mode detecting circuit 313 shown in FIG. 84. In the structure shownin FIG. 87, a response relationship is present between operations oftest control circuit 312 and mode detecting circuit 313. The delay timesof circuits 312 and 313 may be individually adjusted to implement theoperation sequence shown in FIG. 86.

In FIG. 87, test control circuit 312 includes: a test decoder 312 awhich decodes test mode command TM, and generates a signal instructingthe designated operation mode; and a test control signal generatingcircuit 312 b which generates a control signal required for thedesignated operation in accordance with the test operation modeinstructing signal received from test decoder 312 a. FIG. 87 shows, as arepresentative, a shift clock signal SHIFT, a mode instructing signalMODET and update instructing signal UPDATE required in the fourteenthembodiment.

Test control circuit 312 further includes: a one shot pulse generatingcircuit 312 c which generates a one shot pulse signal in response to thestandby state instruction (rising) of operation mode instruction OPC;one shot pulse generating circuits 312 e and 312 f which generate oneshot pulse signals in response to falling of standby mode instructingsignal φST received from mode detecting circuit 313, respectively; an ORcircuit 312 d which receives the pulse signal from one shot pulsegenerating circuit 312 c and shift signal SHIFT from test control signalgenerating circuit 312 b, and produces shift clock signal SFT; an ORcircuit 312 g which receives the pulse signal from one shot pulsegenerating circuit 312 e and mode instructing signal MODET from testcontrol signal generating circuit 312 b, and produces mode instructingsignal MODE; and an OR circuit 312 h which receives the pulse signalfrom one shot pulse generating circuit 312 f and update instructingsignal UPDATE from test control signal generating circuit 312 b, andproduces update instructing signal UPDATE.

Mode detecting circuit 313 includes a set/reset flip-flop 313 a that isreset in response to the standby completion instruction (falling) ofoperation mode instruction command OPC, and is also reset in response tothe falling of the pulse signal from OR circuit 312 d, for generatingstandby mode instructing signal φST. Mode detecting circuit 313 turns onpower supply transistor 314 after flip-flop 321 latches a signal inresponse to shift clock signal SFT.

In the scan test, test decoder 312 a produces the test operation modeinstructing signal in accordance with test mode command TM, and thevarious control signals SFT, MODE and UPDATE are produced in accordancewith this test operation mode instructing signal. During the standbystate in the normal operation mode, shift clock signal SFT, modeinstructing signal MODE and update instructing signal UPDATE areproduced in accordance with the pulse signals generated from one shotpulse generating circuits 312 c, 312 d and 312 f. Accordingly, the scanregisters included in the scan path can be easily utilized as theregister circuits for data saving without making any change to thestructure of the control circuit for test.

In the structure shown in FIG. 87, one shot pulse generating circuit 312f may be supplied with an operation mode instruction OPC as indicated bybroken line, instead of standby mode instructing signal φST. In the scanregister circuit, the through operation and the latch operation may beexecuted in accordance with update instructing signal UPDATE beforepower supply voltage VCL for the internal circuits recovers to thestable state. Even in this case, no problem arises because the powersupply voltage is normally applied to the scan register. Modeinstructing signal MODE is set to the state of selecting the outputsignal of through latch 322 after the power supply to the internalcircuits is stabilized.

After the output signal of through latch 322 is selected for apredetermined period mode by the mode instructing signal MODE, theinternal circuits perform the respective circuit operations (in the caseof the logic circuits), and the internal states return to the samestates as the original states set before transition to the standbystate. In this state, multiplexer 323 selects the output signal of theassociated internal node of the internal circuit at the preceding stage.In this case, if the input circuits operate in synchronization with theclock signal and a transfer gate is arranged at the input/output node,the logical level of the clock signal is merely required to be set, atthe time of the standby exit mode, to such a level that the transfergate for clock synchronization of the internal circuit attains thethrough state.

[First Modification]

FIG. 88 schematically shows a structure of a first modification of thefourteenth embodiment of the present invention. In FIG. 88, a gatetunnel current reducing mechanism 332 is arranged for internal circuitsLK#1-LK#3 of semiconductor device 300. Gate tunnel current reducingmechanism 332 has any of structures for changing the source voltagesand/or deepening the well biases of the MIS transistors included ininternal circuits LK#1-LK#3, and for stopping the supply of powersupply. A test and current control mechanism 330 is provided for gatetunnel current reducing mechanism 332. Test and current controlmechanism 330 operates in accordance with operation mode instruction OPCto activate, in the standby state, gate tunnel current reducingmechanism 332 for reducing the gate tunnel currents in internal circuitsLK#1-LK#3. In the test operation and the normal operation mode, gatetunnel current reducing mechanism 332 is deactivated when internalcircuits LK#1-LK#3 operate. Structures other than the above are thesubstantially same as those shown in FIG. 83. In the test operation, atest signal is scanned through scan path 302.

Alternatively, for reducing the gate tunnel currents of internalcircuits LK#1-LK#3 in the standby state, individual power supplyvoltages may be externally supplied to internal circuits LK#1-LK#3 andscan path 302 separately, rather than external supply of power supplyvoltage VCL to internal circuits LK#1-LK#3.

[Second Modification]

FIG. 89 shows a structure of a second modification of the fourteenthembodiment of the present invention. FIG. 89 shows internal circuit LK#and scan register F# included in scan path 302 as a representative. Ininternal circuit LK#, logic circuit LG includes a CMOS inverter. TheCMOS inverter is formed of MIS transistors PQRa and NQRa each having alow threshold voltage (L-Vth).

A unit circuit UG of scan register F# includes a CMOS inverter. Thisunit circuit UG is a component of each of flip-flop 312 of the scanregister and through latch 322 shown in FIG. 85. In the case wheremultiplexers 320 and 322 are formed of, e.g., tristate inverter buffers,unit circuits UG may likewise be employed in multiplexers 320 and 323. ACMOS inverter in unit circuit UG includes MIS transistors PQRb and NQRbeach having a high threshold voltage (H-Vth). By using the MIStransistor of a high threshold voltage for the MIS transistor formingscan register F#, an off-leak current Ioff in the standby state can bereduced, and the current consumption of the semiconductor device 300 inthe standby state can be further reduced.

[Third Modification]

FIG. 90 shows a structure of third modification of the fourteenthembodiment of the present invention. In internal circuit LK# shown inFIG. 90, each of MIS transistors PQRa and NQRa, which are components oflogic circuit LG, is a (L-Vth) thin film transistor each having athreshold voltage of a small absolute value and a thin gate insulatingfilm. Each of MIS transistors PQRc and NQRc, which are components ofunit circuit UG in scan register F#, is an ITR transistor having a highgate tunnel barrier. In the standby state, therefore, scan register F#in scan path 302 has the gate tunnel current suppressed while holdingthe internal signal, and the current consumption of semiconductor device300 in the standby state can be reduced.

In the structure shown in FIG. 90, the well biases of ITR transistorsPQRc and NQRc in the standby state may be deepened.

[Fourth Modification]

FIG. 91 schematically shows a structure of a fourth modification of thefourteenth embodiment of the present invention. In FIG. 91, asemiconductor device 340 includes boundary scan registers BSR providedfor external input/output terminals, respectively, a test controller 350for controlling transfer of signals/data of boundary scan registers BSR,and an internal circuit 360 coupled to the external input/outputterminals via boundary scan registers BSR. Internal circuit 360 mayinclude the scan path, which allows observation of its internal nodes.

Test controller 350 receives externally supplied input test data, testmode select command TMS, test clock signal TCK and test reset signalTRST, and performs shift operations for successively setting test inputdata TD1 in boundary scan registers BSR. Test controller 350 also latchthe data in boundary scan registers BSR through a scan path SCP formedof these registers BSR, and thereafter performs the shift operation foroutputting output test data therefrom. Further, test controller 350controls the gate tunnel current reducing mechanism, which is providedin internal circuit 360 for reducing the power supply current ofinternal circuit 360 in the standby state, and stores the signals/dataon an internal node of internal circuit 360 in a corresponding boundaryscan register BSR.

FIG. 92 schematically shows a structure of a test controller 350 shownin FIG. 91. In FIG. 92, internal circuit 360 includes an internal logiccircuit 360 a for performing predetermined logical processing, and agate tunnel current reducing mechanism 360 b coupled to internal logiccircuit 360 a. Internal logic circuit 360 a is formed of MIStransistors, and gate tunnel current reducing mechanism 360 b reduces agate tunnel current in the standby state of internal logic circuit 360a. Internal logic circuit 360 a transmits in one direction thesignal/data with scan path SCP including boundary scan registers BSR.Scan path SCP may include a scan path for allowing observation of theinternal nodes of the internal logic circuit 360.

Test controller 350 includes: a TAP (test access port) controller 350 awhich receives test clock signal TCK applied in the test mode, test modeselect signal TMS for selecting and designating the test mode, and testreset signal TRST for resetting the test mode, and produces the internalclock signal for the boundary scan test; an instruction register 350 bwhich receives test data TDI applied bit by bit in serial via a testdata input terminal; an instruction decoder 350 c which decodes aninstruction stored in instruction register 350 b, and produces a controlsignal required for the test; and a control circuit 350 d which producescontrol signals required for the test in accordance with the decodesignal applied from instruction decoder 350 c. Control circuit 350 dcontrols transfer and latch of the signal/data of the boundary scanregisters in scan path SCP, and executes the activation of gate tunnelcurrent reducing mechanism 360 b in the standby state.

The test controller shown in FIG. 92 is a controller compatible with theJTAG test, and usually includes a bypass register for bypassing testdata TDI, and a user-definable register group of which use can bedefined by an user. However, these registers are not shown in FIG. 92.

Test controller 350 includes: a multiplexer (MUX) 350 e which selectseither the output signal/data of scan path SP or the output signal ofthe bypass register (not shown) in accordance with the output signal ofinstruction decoder 350 c; a multiplexer (MUX) 350 f which selects theoutput signal/data of either multiplexer 350 e or instruction register350 b in accordance with the output signal of TAP controller 350 a; anda driver/buffer 350 g which buffers and outputs the output signal/dataof multiplexer 350 f to a test data terminal. In the normal operationmode, test data output terminal TDO is set to a high impedance state.

The test controller shown in FIG. 92 is standardized under the IEEEstandard. In the fourteenth embodiment, instruction decoder 350 c and/orcontrol circuit 350 have a function of receiving operation modeinstruction OPC, to produce signals for controlling the latching ofdata/signal in scan path SCP and of activating the gate tunnel currentreducing mechanism 360 b in the standby state of this semiconductordevice. Control circuit 350 d may have the structure shown in FIG. 87.Instruction decoder 350 c performs a control such that scan path SCPlatches the signals/data on the corresponding nodes in transition to thestandby state, and the signals/data thus latched are transferred to theinternal nodes at the next stage when the standby state is completed.Under the IEEE standard, the boundary scan register can take indata/signal according to an instruction “Capture-DR”, and thesignal/data stored in the boundary scan register can be applied to theinternal node at the next stage according to an instruction “Update-DR”.

The same states as those achieved when these instructions are appliedare produced in instruction decoder 350 c according to operation modeinstruction OPC. In accordance with the signal indicating a decodingresult generated from instruction decoder 350 c, control circuit 350 dproduces control signals required for transfer/latch/update of the data.Operation mode instruction OPC is also applied to instruction decoder350 c and/or control circuit 350 d so that the gate tunnel currentreducing mechanism 360 b is activated for reducing the gate tunnelcurrent in internal logic circuit 360 a during the standby state. Scanpath SCP operates in the same manner as that already described withreference to FIG. 83. Scan path SCP may include not only the boundaryscan registers provided corresponding to the external input/outputterminals but also scan path registers which allows external observationof the internal nodes of internal circuitry.

For reducing the gate tunnel current, the MIS transistors included inscan path SCP may be formed of MIS transistors having large gate tunnelbarriers, and internal logic circuit 360 a is formed of thin filmtransistors. In the semiconductor device which can be subject to theboundary scan test, the leak current due to the gate tunnel current canbe reduced to reduce the current consumption in the standby state.

The structure shown in FIG. 92 can employ all the structures in thefourteenth embodiment already described.

As for the term “the standby state” here, it represents any standbystate in a sleep mode in which the logic circuit stops its operation fora long time, a self-refresh mode in which DRAM or the like isself-refreshed, and an auto-refresh mode in which the refresh operationis repeated a predetermined number of times in accordance with anexternally applied refresh instruction in DRAM or the like, and astandby cycle in the normal operation in which an active cycle and astandby cycle are repeated.

Fifteenth Embodiment

FIG. 93 schematically shows a whole structure of a semiconductor deviceaccording to a fifteenth embodiment of the present invention. FIG. 93shows a Dynamic Random Access Memory (DRAM) as an example of thesemiconductor device. In FIG. 93, this DRAM includes a memory cell array400 having memory cells arranged in rows and columns. Memory cell array400 is divided into a plurality of row blocks RB#1-RB#m and a pluralityof column blocks CB#1-CB#n.

The DRAM further includes: a row address input circuit 402 whichreceives an externally applied row address signal, and produces aninternal row address signal; a row decoder 404 which receives anddecodes the internal row address signal including a block address signalfrom row address input circuit 402; a word line drive and sense-relatedcircuit 406 which includes a word line drive circuit for driving aselected row in a selected block to the selected state in accordancewith the decode signal received from row decoder 404, and asense-related control circuit for controlling the sense amplifiers forsensing and amplifying the data of memory cells in the selected row; acolumn address input circuit 408 which receives an externally appliedcolumn address signal, and produces an internal column address signalincluding a block select signal; a column decoder 410 which performs thedecoding in accordance with the internal column address signal receivedfrom column address input circuit 408, and produces a column selectsignal designating a column to be selected; a data 10 control circuit412 which couples the column selected by column decoder 410 through aninternal IO line to an internal data line for performing input/output ofdata in accordance with the block select address received from columnaddress input circuit 408; and other peripheral circuitry 416 includingan internal voltage generating circuit and a central control circuit forproducing a row-related control signal common to row blocks RB#1-RB#mand a column-related control signal common to column blocks CB#1-CB#n.

Row decoder 404 includes block row decoders provided corresponding torow blocks RB#1-RB#m, respectively, and only a block row decoderprovided corresponding to a row block including the selected rowoperates. The unselected block row decoders maintain the standby state.In column decoder 410, only a block column decoder providedcorresponding to the selected column block performs the decodingoperation. In data 10 control circuit 412, input/output circuit (writedriver/preamplifier) provided corresponding to the selected column isactivated to couple the internal data line to the internal IO lineselected by column decoder 410. Therefore, the block-division operationor a partial activation operation is performed, and row decoder 404,word line drive and sense-related circuit 406, column decoder 410 anddata 10 control circuit 412 control the gate tunnel currents on a blockby block basis.

FIG. 94 schematically shows a structure of a portion corresponding toone row block RB#i (i=1-m) of row decoder 404 and word line drive andsense-related circuit 406 shown in FIG. 93. Referring to FIG. 94, rowblock RB#i is provided with a block row decoder 404 i that is activatedto decode an internal row address signal X when block select signal BSiis active, and a word line driver 406 i that drives an addressed wordline WL in corresponding row block RB#i to the selected state inaccordance with the decode signal of block row decoder 404 i. A senseamplifier band SAB#i is arranged adjacently to row block RB#i. In senseamplifier band SAB#i, sense amplifier circuits are arrangedcorresponding to the columns of the row block RB#i. Sense-relatedcontrol circuit 406 ib controls activation/deactivation of senseamplifier band SAB#i.

Gate tunnel current reducing mechanisms 405 i, 407 i and 409 i areprovided corresponding block row decoder 404 i, word line driver 406 iaand sense-related control circuit 406 ib. These gate tunnel currentreducing mechanisms 405 i, 407 i and 409 i are activated when blockselect signal BSi is in the unselected state, and reduce the gate tunnelcurrents in block row decoder 404 i, word line driver 406 ia andsense-related control circuit 406 ib, respectively when activated. Thesegate tunnel current reducing mechanisms 405 i, 407 i and 409 i arearranged corresponding to each row block. Only for the selected rowblock, block decoder 404 i and word line driver 406 i are activated, andsense-related control circuit 406 i is activated. For the unselected rowblocks, gate tunnel current reducing mechanisms 405 i, 407 i and 409 iare kept active to reduce the gate tunnel currents in the active cycle(in the same manner as in the standby cycle).

If a sense amplifier band is shared between the adjacent row blocks,gate tunnel current reducing mechanism 409 i is also supplied with theblock select signal for the row blocks sharing sense amplifier bandSAB#i. According to the shared sense amplifier structure, in which eachsense amplifier band is shared between adjacent row blocks,sense-related control circuit 406 ib also controls the operations of thebit line isolation gate, the bit line precharge and equalize circuit,and the sense power supply node equalize circuit.

FIG. 95 shows, by way of example, structures of gate tunnel currentreducing mechanisms 405 i and 407 i shown in FIG. 94. In FIG. 95, a unitrow decoder included in block row decoder 404 i includes an NAND decodercircuit 420 a which is enabled to decode internal row decode signal Xwhen block select signal BS is active, and an inverter 420 b whichinverts the output signal of NAND decode circuit 420 a. The power supplynodes of NAND decode circuit 420 a and inverter 420 b are coupled to thepower supply node via a power supply transistor 422. This power supplytransistor 422 is preferably formed of an ITR transistor, and receivescomplementary block select signal /BSi on its gate.

The word line driver includes a level shifter 424 a which converts theoutput signal of inverter 420 b into a signal having an amplitude of thehigh voltage VPP level, and an inverter circuit 424 b which drives acorresponding word line WL in accordance with the output signal of levelshifter 424 a. The gate tunnel current reducing mechanism includes apower supply transistor 426, which is formed of an ITR transistor, andis turned on to supply the high voltage VPP to level shifter 424 a andinverter circuit 424 b in response to complementary block select signal/BSi.

In the structure shown in FIG. 95, power supply transistor 422 isprovided commonly to the unit row decode circuits included in block rowdecoder 404 i, and power supply transistor 426 is provided commonly tothe word line drive circuits included in word line drivers 406 i. In thestandby state or the unselected state, therefore, power supplytransistors 422 and 426 are off so that the power supply voltage is notsupplied to the block row decoder and the word line driver.

In the structure shown in FIG. 95, a word line WL may be formed of ahierarchical word line structure including a main word line ZMWL andsub-word lines SWL. In this case, main word line ZMWL is held at highvoltage VPP level when unselected. In the case of the hierarchical wordline structure, therefore, a structure for interrupting the high voltageis preferably replaced with a structure for deepening a source bias or awell bias, or is preferably replaced with a hierarchical power supplystructure.

FIG. 96 schematically shows a structure of a portion corresponding toone column block CB#j in column decoder 410 and data IO control circuit412 shown in FIG. 93. For column block CB#j, there are arranged: a blockcolumn decoder 410 j which decodes the internal column address signalreceived from column address input circuit 408 shown in FIG. 93 whencolumn block select signal CBj is active, and drives column selectsignal CSL selecting a corresponding column in column block CB#j to theactive state; and a write driver/preamplifier 412 j which writes andreads data onto and from the selected column in column block CB#j. Writedriver and preamplifier 412 j is activated to perform an amplifyingoperation when column block select signal CBj is active, too. Writedriver and preamplifier 412 j is coupled to global data bus GIO, whichis arranged commonly to the memory blocks of column block CB#j with thememory block being the one arranged in the crossing between a row blockand a column block. Write driver and preamplifier 412 j is coupled to aninternal data bus 434. Write driver and preamplifiers 412 j (j=1-n)which are arranged corresponding to the respectively column blocksCB#1-CB#n are coupled commonly to internal data bus 434.

Gate tunnel current reducing mechanisms (ITRCs) 430 j and 432 j areprovided for block column decoder 410 j and write driver/preamplifier412 j, respectively. These gate tunnel current reducing mechanism(ITRCs) 430 j and 432 j are activated, when column block select signalCBj is unselected, to reduce the gate tunnel currents of block columndecoder 410 j as well as write driver/preamplifier 412.

In the structure shown in FIG. 96, the column selecting operation andwrite/read of data are performed in the column block designated bycolumn block select signal CBj. In each unselected column block, blockcolumn decoder 410 as well as write driver/preamplifier 412 maintain theunselected state (standby state). By arranging gate tunnel currentreducing mechanism 430 j and 432 j for each column block, the gatetunnel currents are reduced in an unselected column block of theselected memory array, and the operation current during the activeperiod can be reduced.

[First Modification]

FIG. 97 schematically shows a structure of a first modification of thefifteenth embodiment of the present invention. In FIG. 97, asemiconductor device 444 includes a plurality of banks B#1-B#4, gatetunnel current reducing mechanisms (ITRCs) 444 a-444 d providedcorresponding to respective banks B#1-B#4, and a bank decoder 440 todecode an externally applied bank address signal BA# for producing bankdesignating signals BA1-BA4. Each of banks B#1-B#4 is activated toperform a memory access (row selection or column selection) when acorresponding one of bank designating signals BA1-BA4 is active. Gatetunnel current reducing mechanisms 444 a-444 d are activated to reducethe gate tunnel currents of corresponding banks B#1-B#4 whencorresponding bank address signals BA1-BA4 are inactive, respectively.When bank designating signals BA1-BA4 are in the unselected state,corresponding banks B#1-B#4 are kept in the standby state. Therefore,the gate tunnel current reducing mechanism provided for a unselectedbank in semiconductor device 440 is activated, whereby the leak currentdue to the gate tunnel current can be reduced in semiconductor device444, and therefore the current consumption can be reduced.

As described above, in the fifteenth embodiment of the presentinvention, the gate tunnel currents in the unselected circuits areadapted to be reduced, and thus the current consumption in the circuitoperation or the device active state can be reduced owing to reductionof the gate tunnel currents in the unselected circuit blocks even in theactive cycle, because the gate tunnel leak current can be suppressed.

Sixteenth Embodiment

FIG. 98 schematically shows a structure of a main portion of asemiconductor memory device according to a sixteenth embodiment of thepresent invention. In this sixteenth embodiment, a memory array isdivided into a plurality of row blocks, similarly to the structure shownin FIG. 93. FIG. 98 shows one row block RB#i as a representative. Rowblock RB#i includes a normal memory array NMA#i provided with normalword lines NWL, and a spare memory array SMA#i provided with spare wordlines SWL.

A normal row select circuit 450 is provided for normal memory arrayNMA#i, and a spare row select circuit 452 is provided for spare memoryarray SMA#i. Normal row select circuit 450 includes a normal row decoderand a normal word line drive circuit for driving a selected normal wordline NWL in accordance with the output signal of the normal row decoder.Likewise, spare row select circuit 452 includes a spare row decoder anda spare word line drive circuit for driving spare word line SWL to theselected state in accordance with the output signal of spare rowdecoder.

Gate tunnel current reducing mechanisms (ITRCs) 454 and 456 are providedfor normal row select circuit 450 and spare row select circuit 452,respectively. Gate tunnel current reducing mechanisms 454 and 456 in theactive state reduce the gate tunnel currents in the correspondingcircuits, respectively.

For row block RB#i, there is arranged a spare determining circuit 458for determining which one of normal word line NWL and spare word lineSWL is to be selected. Spare determining circuit 458 stores an addressof a defective row in normal memory array NMA#1, and is activated whenblock select signal BS is activated to designate the row block RB#i.Spare determining circuit 458, when activated, compares address signal Xapplied thereto with the stored address of the defective memory cell,and activates one of a normal row enable signal NRE and a spare rowenable signal SRE in accordance with the result of determination. Normalrow enable signal NRE controls activation/deactivation of normal rowselect circuit 450, and spare row enable signal SRE controlsactivation/deactivation of spare row select circuit 452.

Normal row enable signal NRE is usually applied to a normal word linedrive circuit, and normal row select circuit 450 decodes row addresssignal X applied thereto when block select signal BS is in the selectedstate. During the standby state, normal row enable signal NRE is atH-level. Spare row enable signal SRE is at L-level during the standbystate, and the spare word line is driven to the selected state whenspare row enable signal SRE is active.

Gate tunnel current reducing mechanism (ITRC) 454 provided for normalrow select circuit 450 is made inactive when a gate circuit 460receiving normal row enable signal NRE and block select signal BSgenerates an output signal at H-level. Gate tunnel current reducingmechanism (ITRC) 454 is activated to reduce the gate tunnel current innormal row select circuit 450 when at least one of block select signalBS and normal row enable signal NRE is inactive or at L-level. In FIG.98, gate circuit 450 is depicted being formed of an NAND circuitreceiving block select signal BS and normal row enable signal NRE. Thisis because normal row enable signal NRE is set to H-level in the standbystate.

Gate tunnel current reducing mechanism (ITRC) 456 provided for spare rowselect circuit 452 is activated to reduce the gate tunnel current ofspare row select circuit 452 when spare row enable signal SRE isinactive. Spare row enable signal SRE is fixed to L-level in the standbystate and unselected state (i.e., in access to a normal memory cell).

In the structure shown in FIG. 98, spare determining circuit 458 isprovided corresponding to each row block RB#i, and the sparedetermination is executed on a row block by row block basis. When aspare word line is to be used in the selected row block, the gate tunnelcurrent in normal row select circuit 450 is reduced. When normal wordline NWL is to be used (accessed), the gate tunnel current in spare rowselect circuit 452 is reduced. In the selected row block, therefore, thegate tunnel currents of the unselected circuits can be reduced, and thecurrent consumption during the active period can be reduced. In anunselected row block, gate tunnel current reducing mechanisms 454 and456 are both activated.

[First Modification]

FIG. 99 schematically shows a structure of a first modification of thesixteenth embodiment of the present invention. In FIG. 99, a memoryarray MA is divided into a plurality of row blocks RB#1-RB#m. Memoryarray MA is also divided into normal column blocks including normalcolumns, and spare column blocks including spare columns. These normaland spare column blocks are arranged corresponding to each other in therow blocks. Normal column blocks NC#1-NC#m as well as spare columnblocks SPC#1-SPC#m are arranged. Row block RB#i includes normal columnblock NC#i and spare column block SPC#i.

A word line is arranged commonly to normal column block NC#i and sparecolumn block SPC#i. Therefore, when one row block is selected, a rowdecoder (not shown) selects a row in the normal column block and thespare column block in the selected row block.

A normal column decoder 470 is provided commonly to normal column blocksNC#1-NC#m, and a spare column decoder 471 is provided commonly to sparecolumn blocks SPC#1-SPC#m. A normal read/write circuit 472 is providedfor performing data access to a normal column selected by normal columndecoder 470. Also, a spare read/write circuit 473 is provided forperforming data access to a spare column selected by spare columndecoder 471.

For determining which one of the normal column and the spare column isto be accessed, a column spare determining circuit 474 is provided.Column spare determining circuit 474 activates one of normal columnenable signal NCE and spare column enable signal SCE in accordance withmatch/mismatch between an applied column address signal Y and thedefective column address. Usually, normal column enable signal NCE isset to H-level during the normal column access and the standby state,similarly to normal row enable signal NRE. Spare column enable signalSCE is set to the active state of H-level only when a spare column is tobe accessed.

Gate tunnel current reducing mechanisms (ITRCs) 475 and 476 are providedfor normal column decoder 470 and normal read/write circuit 472,respectively. Gate tunnel current reducing mechanisms (ITRCs) 477 and478 are provided for spare column decoder 471 and spare read/writecircuit 473, respectively. These gate tunnel current reducing mechanisms475 and 476 reduce the gate tunnel currents of normal column decoder 470and normal read/write circuit 472, respectively, when an output signalof a gate circuit 480 receiving a column access activating signal CASand normal column enable signal NCE is active or at H-level. Gatecircuit 480 is shown being formed of an NAND circuit in FIG. 99, basedon the assumption that each of column access activating signal CAS andnormal column enable signal NCE is at H-level when activated. Therefore,the output signal of gate circuit 480 is deactivated (L-level) when thecolumn access of column selection and the data access (write/read)start, and a normal column address is designated. Responsively, gatetunnel current reducing mechanisms 475 and 476 are deactivated to stopthe gate tunnel current reducing operations for normal column decoder470 and normal read/write circuit 472, respectively.

Gate tunnel current reducing mechanisms (ITRCs) 477 and 478 provided forspare column decoder 471 and spare read/write circuit 473 are activatedto reduce the gate tunnel currents of spare column decoder 471 and spareread write circuit 473 when spare column enable signal SCE is inactive.Spare column enable signal SCE is held inactive (L-level) during thestandby state and the normal column access.

Therefore, the gate tunnel current for inactive circuits is reducedduring the column access, and the current consumption during the columnaccess period can be reduced.

[Second Modification]

FIG. 100 schematically shows a structure of a second modification of thesixteenth embodiment of the present invention. In FIG. 100, a memoryarray is divided into a plurality of row blocks 504 a-504 m. Each of rowblocks 504 a-504 m includes a normal row block 501 with normal wordlines, and a spare row block 502 with spare word lines. In the structureshown in FIG. 100, a defective row is repaired in units of row blocks.Sense amplifier bands 500 a-500 n are arranged adjacent in the columndirection to row blocks 504 a-504 m, respectively. Sense amplifier bands500 a-500 n shared between adjacent row blocks.

Row decoders RD including word line drive circuits are arranged forrespective row blocks 504 a-504 m. Each row decoder RD includes a normalrow decoder (RD) arranged corresponding to normal row block 501 and aspare row decoder (RD) arranged corresponding to spare row block 502.

For sense amplifier bands 500 a-500 n, column decoders CD are arrangedfor producing column select signals, respectively. The column selectsignals produced by column decoders CD are transmitted via column selectlines extending in the row direction within corresponding senseamplifier bands 500 a-500 n. Accordingly, column decoder CDsimultaneously performs the column selection in the spare column blockand the column selection in the normal column block within a row block.Column decoder CD is not supplied with a result of the column sparedetermination. When a corresponding block select signal is active in thecolumn access, the column decode operation is executed in accordancewith the column access instructing (activating) signal CACT.

A column gate tunnel current reducing mechanism CITRC is arrangedcorresponding to column decoder CD, and a row gate tunnel currentreducing mechanism RITRC is arranged for row decoder RD. Row gate tunnelcurrent reducing mechanism RITRC includes a normal gate tunnel currentreducing mechanism NITRC provided for normal row decoder (RD) and aspare row gate tunnel current reducing mechanism SITRC provided forspare row decoder (RD).

For row decoders RD, there are arranged row spare determining circuits506 a-506 m, respectively. Each of row spare determining circuit 506a-506 m is supplied with a corresponding block select signal in blockselect signals BS<m:1>. The block select signals BS<m:1> are applied tocorresponding column gate tunnel current reducing mechanisms CITRCprovided corresponding to column decoders CD.

A normal read/write circuit 508 is provided for the normal columnblocks, and a spare read/write (R/W) circuit 509 is provided for a sparecolumn blocks. These normal read/write circuit 508 and spare read/write(R/W) circuit 509 operate in parallel in the column access operation.

In the memory array, a global data bus of multiple bits is coupled inparallel to normal read/write circuit 508, and a defective column isreplaced on a global data line basis. For repairing a defective column,there are arranged: a column redundant control circuit 510 which isactivated to decode row block address signal RBA and produce data lineselect signal SEL when column access instructing signal CACT is active;and a multiplexer (MUX) 511 which selectively couples normal read/writecircuit 508 and spare read/write circuit 509 to an input/output circuit512 in accordance with data line select signal SEL applied from columnredundant control circuit 510. In column redundant control circuit 510,programming of defective column addresses is individually performed foreach row block, and the global data line which is connected to thedefective column in the selected row block is replaced with the spareglobal data line in accordance with row block address signal RBA.

Since normal read/write circuit 508 and spare read/write circuit 509operate in parallel, gate tunnel current reducing mechanism (ITRC) 513is provided commonly to these normal read/write circuit 508 and spareread/write (R/W) circuit 509. This gate tunnel current reducingmechanism 513 reduces the gate tunnel currents of normal read/writecircuit 508 and spare read/write circuit 509 when column accessinstructing signal CACT is inactive. When a column access starts, theoperation of reducing the gate tunnel currents of normal and spareread/write circuits 508 and 509 stops, and these normal and spareread/write circuits 508 and 509 operate fast.

In the structure shown in FIG. 100, the gate tunnel currents of columndecoder CD and row decoder RD are controlled in accordance with blockselect signals BS<m:1> and the result of determination by acorresponding one of row spare determining circuits 506 a-506 m. Whenthe normal row block is to be accessed in a selected row block, thecorresponding spare gate tunnel current reducing mechanism SITRC is heldin substantially the same state as that in the standby state, so thatthe gate tunnel current of corresponding spare row decoder (RD) isreduced.

When a spare word line is to be accessed in the selected row block, thecorresponding normal gate tunnel current reducing mechanism NITRCmaintains substantially the same state as that in the standby state, sothat the gate tunnel current of the corresponding normal row decoder(RD) is reduced.

In the structure shown in FIG. 100, therefore, control of the gatetunnel current is performed on a row block basis and on a normal/spareblock basis, and the gate tunnel current reducing operation is stoppedonly for the circuit to be operated. Therefore, the current consumptionduring the active period (period of memory cell selecting operation) isreduced.

Activation and deactivation of column gate tunnel current reducingmechanism CITRC for column decoder CD are controlled in accordance withblock select signals BS<m:1> produced from row block address signal RBA.However, column gate tunnel current reducing mechanism CITRC may beconfigured to receive both block select signals BS<m:1> and columnaccess instructing signal CACT, to stop its gate tunnel current reducingoperation only when both the received signals are in the selected state.

[Third Modification]

FIG. 101A schematically shows a structure of a main portion of a thirdmodification of the sixteenth embodiment of the present invention. FIG.101A shows a structure of only a row-related circuit for one row block.

In FIG. 101A, the row-related circuit includes: an address input buffer552 which latches word line address signal X in accordance with a rowaddress latch enable signal RAL; a row decoder 554 which decodesinternal word line address signal X applied from address input buffer552 in accordance with row decoder enable signal RADE; a normal wordline driver 556 which drives a normal word line NWL to the selectedstate in accordance with word line drive timing signal RXT and theoutput signal of row decoder 554; a row block decoder 558 which decodesrow block address signal RBA; a row spare determining circuit 560 whichis activated in accordance with block select signal BSF applied from rowbock decoder 558, and determines whether word line address signal Xdesignates a defective row or not when activated; a latch circuit 562which latches spare row enable signal SREF applied from row sparedetermining circuit 560 in accordance with row decoder enable signalRADE; and a spare word line driver 564 which is activated in accordancewith spare row enable signal SRE applied from latch circuit 562, anddrives a spare word line SWL to the selected state in response to wordline drive timing signal RXT when activated.

This row-related circuit further includes a latch circuit 566 which isactivated in accordance with row decoder enable signal RADE to latchblock select signal BSF applied from row block decoder 558 and normalrow enable signal NREF applied from row spare determining circuit 560,and generate block select signal BS and normal row enable signal NRE torow decoder 554. Normal row enable signal NRE applied from latch circuit566 may be applied to normal word line driver 556.

Row-related control circuit 550 produces row address latch enable signalRAL, row address decoder enable signal RADE and word line drive timingsignal RXT in a predetermined sequence when row access activating signalRACT is active. Row-related control circuit 550 and address input buffer552 are provided commonly to a plurality of row blocks. An operation ofthe structure shown in FIG. 101A will now be described with reference toa signal waveform of FIG. 101B.

When row access activating signal RACT is driven to the active state ofH-level, row address latch enable signal RAL, row address decoder enablesignal RADE and word line drive timing signal RXT are successivelyactivated in a predetermined sequence. Before the activation of rowaccess activating signal RACT, word line address signal X and row blockaddress signal RBA are applied. Row block decoder 558 and row sparedetermining circuit 560 operate asynchronously to row access activatingsignal RACT, and perform the decoding operation and the determiningoperation, respectively. In other words, the row spare determination isperformed utilizing the setup periods of address signals X and RBA withrespect to row access activating signal RACT.

In accordance with block select signal BSF generated from row blockdecoder 558, the spare determining operation is performed in theselected row block. In accordance with the spare determination result,normal row enable signal NREF and spare row enable signal SREF are setto the states representing the result of spare determination,respectively. Therefore, normal row enable signal NREF and spare rowenable signal SREF generated from row spare determining circuit 560 aremade definite before activation of row access activating signal RACT.

Then, latch circuits 566 and 562 take in and latch the applied signalsin accordance with activation of row address decode enable signal RADE.Accordingly, row decoder 554 is supplied with block select signal BS andnormal enable signal NRE. When a normal word line is designated in theselected row block, row decoder 554 performs the decoding operation, andthen normal word line driver 556 drives the normal word line NWL to theselected state.

When a defective word line is addressed in the selected row block, rowdecoder 554 does not perform the decoding operation, and maintains thestandby state. Normal word line driver 556 also maintains the standbystate. When the defective word line is addressed, the spare row enablesignal SREF from row spare determining circuit 560 becomes active, latchcircuit 562 enters the latch state in accordance with row addressdecoder enable signal RADE, and spare word line driver 564 drives spareword line SWL to the selected state in accordance with word line drivetiming signal RXT.

Accordingly, the result of spare determination is in the definite statebefore activation of row access activating signal RACT or beforeactivation of row address decoder enable signal RADE at the latest, andthe period required for the spare determination within the active periodcan be reduced, and thus, the current consumption of the circuits, whichare held inactive in the normal and spare row decoders, can be reduced,because corresponding gate tunnel current reducing mechanisms are drivento the active state.

In the case of a standard DRAM, this row access activating signal RACTis produced in accordance with row address strobe signal /RAS. In thecase of a synchronous DRAM operating synchronously with the clocksignal, an active command is applied, and the internal active state ismaintained until reception of a subsequent precharge command.

In the case of the clock synchronous DRAM, latch circuits 566 and 562may be configured to transfer corresponding signals in synchronizationwith cock signal CLK.

Such a structure may be employed that word line address signal X isapplied to row spare determining circuit 560 and row decoder 554, andblock select signal BSF from row block decoder 558 is transferred insynchronization with the clock signal for activating row decoder 554 andtransfer of the output signal of row spare determining circuit 560.

In any of the above structures, the setup period of the address signalis utilized for performing the row spare determination.

In the structure shown in FIG. 101A, row block decoder 558 and row sparedetermining circuit 560 operate statically. However, row block decoder558 and row spare determining circuit 560 may be temporarily reset inresponse to the deactivation of row access activating signal RACT.

In the structure shown in FIG. 101A, one spare word line SWL is providedin the spare row block. In the case where a plurality of spare wordlines SWL are provided in each row block, row spare determining circuit560 is configured to include spare determining circuits corresponding torespective spare sub-word lines, with spare word lines being related tothe spare determining circuits in a one-to-one relationship. In thiscase, normal row enable signal NREF is produced by NOR operation onoutput signals of the plurality of spare determining circuits.

[Fourth Modification]

FIG. 102 schematically shows a structure of a fourth modification of thesixteenth embodiment of the present invention. FIG. 102 showscolumn-related circuitry.

In FIG. 102, the column-related circuit includes: a column-relatedcontrol circuit 578 which is responsive to activation of column accessinstructing signal CACT for producing column address latch enable signalCAL and column address decoder enable signal CADE in a predeterminedsequence; a column address input buffer 570 which takes in and latchescolumn address signal Y in response to column address latch enablesignal CAL; a column spare determining circuit 572 which is activated inresponse to activation of row access activating signal RACT, toincorporate column address signal Y for performing the column sparedetermination; a normal column decoder 573 which is responsive toactivation of column address decoder enable signal CADE for latchingnormal column enable signal NCE received from column spare determiningcircuit 572, and decoding the column address signal received from columnaddress input buffer 570; and a spare column decoder 576 which latchesspare column enable signal SCE received from column spare determiningcircuit 572 in response to activation of column address decoder enablesignal CADE, and produces spare column select signal CSL.

Spare column decoder 576 merely drives spare column select line SCSL tothe selected state in accordance with spare column enable signal SCE. Inthe case where a plurality of spare column lines are provided, columnspare determining circuit 572 is adapted to include a plurality ofprogram circuits for storing a plurality of address of defectivecolumns, with these column program circuits corresponding to therespective spare column select lines SCSL.

Normal column decoder 574 and spare column decoder 576 drive normalcolumn select line NCSL and spare column select line SCSL to theselected state in accordance with column address decoder enable signalCADE, respectively. Column spare determining circuit 572 performs thespare determining operation asynchronously to column access activatingsignal CACT, as shown in FIG. 103. Accordingly, at the start of decodingby normal column decoder 574, column spare determining circuit 572 hasalready completed its determining operation. Therefore, the columnselecting operation can be internally started at a faster timing, andthe activation/deactivation of the gate tunnel current reducingmechanisms provided for normal and spare column decoders 574 and 576 canbe controlled at a faster timing.

Since the time for switching the states of gate tunnel current reducingmechanism is not present within the active period, the currentconsumption caused by this switching can be eliminated from the activeperiod, and the current consumption in the active period can be reduced.

In the structure shown in FIG. 102, column access instruction(activation) signal CACT may be produced in accordance with columnaddress strobe signal /CAS, or may be produced in accordance with thecolumn access command, as is done in the clock synchronous DRAM. In thecase of the clock synchronous DRAM, the determination result of columnspare determining circuit 572 may be transferred in synchronization withclock signal CLK.

In the structures shown in FIGS. 101A and 102, internal operations areperformed in accordance with access activating signals RACT and CACT,and the gate tunnel current reducing mechanisms are selectivelyactivated. Alternatively, the gate tunnel current reducing mechanismsmay be configured to be switched in the state asynchronously to theseaccess activating signals RACT and CACT. More specifically, in FIG.101A, block select signal BSF generated from row block decoder 558 aswell as spare and normal row enable signals SREF and NREF generated fromrow spare determining circuit 560 may be adapted to be applied to thecorresponding gate tunnel current reducing mechanisms.

In the structure shown in FIG. 100, the normal and spare row blocks arearranged within the row block. Alternatively, a single spare row blockmay be provided commonly to a plurality of normal row blocks. In thiscase, the activation/deactivation and the gate tunnel current of thenormal sense amplifiers are controlled independently of those of thespare sense amplifiers.

According to the sixteenth embodiment of the present invention, asdescribed above, in the normal/spare memory cell redundant structure,the gate tunnel current reducing mechanism for the access path in theunselected state is held active. Thus, the leak current due to the gatetunnel current can be reduced, and thereby the current consumption canbe reduced during the active period of this semiconductor memory device.

According to the present invention, as described above, the ITRtransistors or the MIS transistors which can have large gate tunnelbarriers are used in the portions where gate tunnel current may cause aproblem, so that the gate tunnel leak current can be efficientlysuppressed, and the current consumption can be reduced.

Although the present invention has been described and illustrated indetail, it is clearly understood that the same is by way of illustrationand example only and is not to be taken by way of limitation, the spiritand scope of the present invention being limited only by the terms ofthe appended claims.

1. A semiconductor device comprising: a first power source node; a logicgate including, as a component thereof, an insulated gate field effecttransistor having a first gate tunnel barrier, for receiving a voltageon a first power source line as an operation power supply voltage andperforming a predetermined operation; and a first switching transistorconnected between said first power source node and said first powersource line, formed of an insulated gate field effect transistor havinga gate tunnel barrier larger than said first gate tunnel barrier, andselectively turned on in response to an operation mode instructingsignal instructing an operation mode of said logic gate.
 2. Thesemiconductor device according to claim 1, wherein said first gatetunnel barrier is equivalent to a gate tunnel barrier of a silicon oxidefilm having a thickness of 3 nanometers at most.
 3. The semiconductordevice according to claim 1, wherein said insulated gate field effecttransistor of said logic gate has a gate insulating film of 3 nanometersat most in thickness. 4-34. (canceled)